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hazard-detection

Here are 12 public repositories matching this topic...

mr-bat / Computer_Architecture_Lab

MIPS implementation

caching mips sram hazard-detection data-forward

Updated May 27, 2019
Verilog

sushi0706 / mips-pipeline-processor

5-stage pipelined 32-bit MIPS processor

pipeline verilog computer-architecture hazard-detection mips-processor data-forwarding

Updated Jul 20, 2024
Verilog

DoniaGameel / Pipelined-Processor-using-verilog

Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor

assembler hazard-detection alu branch-prediction control-unit pipelined-processors full-forwarding

Updated Jan 29, 2023
Verilog

FarrukhAijaz / Single-Cycle-Multi-Cycle-and-Pipeline-ARM-Based-Processor-Design

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

processor-architecture arm processor verilog mcu computer-architecture hazard-detection pipeline-processor verilog-hdl 32-bit arm32 pipline processor-design single-cycle-processor multi-cycle-processor multi-cycle-cpu datapath-design

Updated Jun 28, 2024
Verilog

Mahekkumar-Varasada / 5-Stage-MIPS-Pipelined-with-Hazard-Mitigation

The design of modules to reduce pipeline Hazards, as well as the MIPS processor architecture. It implements some instruction set, instruction and data memory, 32 general- purpose registers, an Arithmetic Logical Unit (ALU) for basic operation, a forwarding unit and hazards detecting unit.

mips computer-architecture hazard-detection mips-architecture mips32 nirma-university forwarding-unit control-hazards 5-stage-pipelined-processor hazard-mitigation

Updated Oct 27, 2024
Verilog

arianhaddadi / ARM-Processor-32-bit

A 32-bit Arm Processor Using Verilog HDL With Hazard Detection, Forwarding Unit, SRAM Memory & A 2-Way Set-Associative Cache.

cache sram hazard-detection arm32 forwarding-unit

Updated Jul 22, 2021
Verilog

amaurilopez90 / LEGv8-CPU

Verilog Implementation of an ARM LEGv8 CPU

arm computer-architecture hazard-detection pipeline-cpu legv8-arm forwarding-unit

Updated Aug 14, 2018
Verilog

williamqwu / VE370-Pipelined-Processor

An MIPS pipelined processor with hazard detection for the course VE370 (FA2020) of UM-SJTU JI.

cpu pipeline hazard-detection computer-organisation-architechure pipelined-processors

Updated Dec 28, 2020
Verilog

ARM-Processor

kalhorghazal / ARM-Processor

ARM Processor, Computer Architecture laboratory, University of Tehran

pipeline forwarding computer-architecture hazard-detection verilog-hdl arm-processor

Updated Sep 10, 2021
Verilog

nicolavianello95 / RISC-V

Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection, Branch Target Buffer using LRU replacement policy, absolute value custom instruction.

asic cpu vhdl forwarding hazard-detection risc-v branch-target-buffer

Updated Apr 12, 2020
Verilog

nxbyte / ARM-LEGv8

Verilog Implementation of an ARM LEGv8 CPU

arm verilog xilinx isa vivado hazard-detection ldr pipeline-cpu single-cycle hennessy patterson legv8-arm multi-cycle arm-legv8-simulator forwarding-unit

Updated Oct 3, 2018
Verilog

mhyousefi / MIPS-pipeline-processor

A pipelined implementation of the MIPS processor featuring hazard detection as well as forwarding

pipeline verilog computer-architecture hazard-detection mips-processor forwarding-unit

Updated May 20, 2022
Verilog

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