Formal AXI verification properties from the eXpect framework for secure SoC validation

Project for Hardware and Embedded Security class in Cybersecurity course.

RTL module to verify legal signature IDs using Verilog

A 64-bit custom hash function based on the AES inverse S-Box, implemented in both Python (golden model) and SystemVerilog RTL for FPGA. Developed as part of the Hardware and Embedded Security course at the University of Pisa.