Repository to store all design and testbench files for Senior Design

Formally proven secure design of the RISC-V core BOOM (Berkeley Out-of-Order Machine) w.r.t. transient execution attacks (e.g., Meltdown and Spectre)

Reproduction of https://github.com/DfX-NYUAD/GNNUnlock

This repository contains the hardware layout and verification IP for the implementation of Okapi in the RISC-V core BOOM.

This project is a modified verison of the OpenRISC 1200 open-source processor, designed to estimate the feasibility of using an On-Chip Software Obfuscator to reduce the controllability over software activated Hardware Trojans.

Supporting material for our RL-based Trojan insertion work at CCS 2022.

This repository contains exercises and labs for the "Hardware & Embedded Security" course in the Master's program in Cybersecurity at Politecnico di Torino.

An AES-128 encryption module in CTR mode with APB interface, implemented in Verilog for FPGA-based secure data communication systems.

.FirmEx is a unified framework for embedded device security that combines automated firmware extraction with real-time sensor anomaly detection. This work was accepted at IEEE Intelligent Computing and Systems at the Edge (ICEEdge) Student Forum 2025

Some generic probabilistic methodologies to identify hardware trojans in arbitrary hardware designs

This repository contains exercises and laboratories related to the Hardware and Embedded Security Course at @polito, where we mainly write code for hardware description like Verilog and VHDL