Janus astrophysics Simulator implemented on ZU19EG Ultrascale+

Janus Algorithm in C++ version without FPGA acceleration.

UltraZed Development

Visual System Integrator - Accelerate your embedded development

Squeezenet V1.1 on Cyclone V SoC-FPGA at 450ms/image, 20x faster than ARM A9 processor alone. A project for 2017 Innovate FPGA design contest.

A crypto accelerator written for HLS to an FPGA that actually makes it slower than running it on your computer

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

An OpenCL-based FPGA Accelerator for Convolutional Neural Networks

Open Source Specialized Computing Stack for Accelerating Deep Neural Networks.

Small-scale Tensor Processing Unit built on an FPGA

TURBOdeb #xohw19-157 #TuringBombe #Enigma

This project implements a convolution kernel based on vivado HLS on zcu104

Hardware-accelerated sorting algorithm

Network Packet classification on FPGA

Synthesizeable VHDL and Verilog implementation of 64-point FFT/IFFT Processor with Q4.12 Fixed Point Data Format.

Accelerating a Classic 3D Video Game (The DOOM) on Heterogeneous Reconfigurable MPSoCs

Co-processor for whole genome alignment

A FPGA Based Square Root Approximation Coprocessor

Lenet for MNIST handwritten digit recognition using Vivado hls tool

OPAE porting to Xilinx FPGA devices.