"100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
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Jul 9, 2023 - Verilog
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digital-system-design
Here are 22 public repositories matching this topic...
Final Project for Digital Systems Design Course, Fall 2020
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Jul 20, 2022 - Verilog
Implementation of a low-pass FIR filter in Verilog HDL.
matlab digital-signal-processing verilog-hdl fir-filters digital-system-design digital-systems-design low-pass-filters
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Apr 12, 2024 - Verilog
Fixed Point FPGA-based Hardware Implementation of a 32-tap Low Pass FIR Filter for Audio Applications
fpga verilog digital-signal-processing verilog-hdl audio-processing equalizer filter-design xilinx-vivado fir-filters audio-equalizer digital-system-design digital-signal-processing-filters digital-systems-design
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Dec 28, 2024 - Verilog
Digital Systems Design - Spring 2023 - Sharif University of Technology
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Apr 2, 2024 - Verilog
Direct Digital Synthesizer for Generating Sine Waves using Verilog HDL
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Mar 29, 2024 - Verilog
Verilog implementation of the basic structure of an FPGA
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May 22, 2024 - Verilog
Lab projects using Verilog HDL
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Apr 26, 2022 - Verilog
Implementation of a FIFO structure for Digital Systems | Written in Verilog HDL
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Mar 26, 2024 - Verilog
Home automation simulation project created for the UofT ECE241 course. Worked on by Harsh Grover and Joonseo Park. More details in README
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Jan 19, 2024 - Verilog
This is a simple project that shows how to multiply two 8x8 matrixes in Verilog.
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May 17, 2024 - Verilog
Digital System Design Verilog Implementation
verilog logic-gates fifo lifo adders verilog-simulator subtractor verilog-code digital-system-design
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Feb 26, 2022 - Verilog
Academic Lab Course of the 27th batch of Computer Science & Engineering | University of Rajshahi - 🇧🇩
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Apr 7, 2024 - Verilog
👾 My studies with Verilog and notions of digital systems.
verilog icarus-verilog hdl verilog-hdl digital-systems verilog-project verilog-code digital-system-design verilog-examples digital-systems-design digital-systems-fundamentals
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Nov 2, 2022 - Verilog
Advanced Pheripheral Bus design using verilog HDL
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Sep 7, 2021 - Verilog
The Electronic Voting Machine (EVM) is a digital voting system implemented using Verilog, designed to securely and efficiently simulate an election process. The machine supports voting for multiple candidates, ensures vote authenticity, provides real-time vote counts.
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Feb 12, 2025 - Verilog
verilog model of a 32 bit RISC-V processor core supporting the RV32I instruction set
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Feb 12, 2024 - Verilog
This code is for the final project of the Digital System Design course taught by Dr.Farshad Baharvand on the Fall semester of 2020
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Oct 21, 2023 - Verilog
N-bit adder implementations (Ripple Carry, Carry Lookahead, and Prefix) with synthesis using Cadence Genus. Area, power, and delay comparisons are provided for N = 4, 8, 16, 32, and 64.
delay comparison power synthesis area vlsi adder cadence-virtuoso cadence digital-design digital-system-design ripple-carry-adder prefix-adder carry-lookahead-adder
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Jun 11, 2025 - Verilog
A simple example on textbook
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Apr 28, 2024 - Verilog
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