A Reconfigurable RISC-V Core for Approximate Computing

Design of Banked Memory Access Unit for Load Store Instructions of a 32-bit Vector Processor

In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.

Verilog implementation of 8-bit CISC Processor using 4 phase clocking scheme

Aggreage of my past CPU designs.

The purpose of this project is to design, simulate, implement, and verify a simpleRISC Computer (Mini SRC) consisting of a simple RISC processor, memory, and I/O.

Sample Verilog codes for digital circuits

This is an implementation of a simple CPU in Logisim and Verilog.

This project involves the creation of a single-cycle MIPS CPU design using Verilog. The single-cycle microarchitecture is characterized by executing an entire instruction in one clock cycle. The project delves into the intricacies of designing and implementing a simplified MIPS CPU, providing insights into its fundamental components.

FISC - Flexible Instruction Set Computer - Is the new Instruction Set Architecture inspired by ARMv8 and x86-64

a simple risc processor

A Verilog-implemented MIPS32 pipelined processor featuring a 2-bit branch predictor and an exception handling unit, supporting over 50 instructions including arithmetic, logic, branch, memory, and control operations.

Verilog implementation of 16-bit RISC Processor with 4-stage pipeline

Sngle-cycle, Multi-cycle and Pipeline MIPS implementations; Spring 2022

Verilog CPU Design Project, ELEC 374 - Digital Systems Engineering

32-bit 5-stage pipelined RISC-V CPU (RV32I) in Verilog HDL. Supports ADD, SUB, AND, OR, LW, SW, BEQ, BNE with hazard handling (forwarding, stalls, flushes). Verified using testbenches and GTKWave, achieving CPI ≈ 1.0 on hazard-free execution.

An 8-bit CPU with a custom ISA, designed from scratch in Verilog, and its complete assembler toolchain developed in C++.

Single-cycle and multi-cycle implementation of a subset of MIPS instruction set

HITSZ_2025_Summer_CS_miniLA_cpu_design

Fully functional RISC-V compatible multicycle CPU built in Verilog. Includes ALU, datapath, FSM controller, memory, and testbenches.