This is an implementation of a simple CPU in Logisim and Verilog.
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Updated
Jan 11, 2019 - Verilog
This is an implementation of a simple CPU in Logisim and Verilog.
Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.
🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.
simple 8-bit single-cycle processor which includes an ALU, a register file and control logic, using Verilog HDL.
16 bit processor designed in logisim
Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor
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