RISC-V CPU Base Integer 32 bit ISA Implementation in Verilog HDL (Singlecycle, Multicycle, Pipelined). Update with more extension functionalities in the future.

A 32 Bit RISC-V Processor Implementation in Verilog

🧠 Pipelined Processor is to design, implement and test a Harvard (separate memories for data and instructions), RISC-like, five-stages pipeline processor.

A 5-stage pipelined 64-bit ARM processor; implemented in SystemVerilog

Laboratorio 1 de la materia de Arquitectura del Computador de la Licenciatura en Ciencias de la Computación de FAMAF (UNC)

Processor designed to execute machine code instructions generated using an MIPS assembler. The assembler takes the machine code as input and performs the required operations.

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

A ModelSim project that implements a MIPS pipelined CPU in Verilog, enhancing efficiency through pipelining based on single-cycle CPU concepts.

5-Stage Pipelined Processor for RV32I with Hazard Control and Branch Prediction.

A digital design project for a MIPS Reduced Instruction Set Computer (RISC) pipelined processor design that has a 5 stage basic pipeline and supports 32-bit MIPS instructions with an 8-bit wide datapath, on a 256x32 ROM and 256x8 RAM, implemented through structural VHDL