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adder-subtractor

Here are 5 public repositories matching this topic...

gabrielganzer / VHDL-DesignSynthesis

Design & Synthesis of several digital circuits in VHDL and Verilog. Scripting in TCL, simulation with Intel® ModelSim®, and synthesis under Synopsys® DC Ultra™.

polito vhdl scripts tcl rtl verilog synthesis digital-design control-unit subtractor physical-design booth-multiplier register-file windowed-register-file adder-subtractor

Updated Jan 24, 2021
Verilog

Vedant-02 / Verilog-HDL-Lab-Experiments

Verilog, standardized as IEEE 1364, is a hardware description language used to model electronic systems. This repository consists of Verilog HDL lab experiments conducted in course EEL2020 Digitial Design at IIT Jodhpur

Updated Oct 23, 2022
Verilog

CedricRev / simple-calculator-verilog

An 8-bit calculator that can multiply, add and subtract. Created and simulated in Quartus Prime and physically implemented in DEC-SOC1 FPGA.

verilog multiplexer multiplier full-adder adder-subtractor

Updated Jan 26, 2024
Verilog

Shakil-RU / Verilog_HDL

"Verilog_HDL" repository contains hardware description language (HDL) code written in Verilog for various digital logic and electronic designs."

counter multiplexer comparator adder encoder-decoder flipflop adder-subtractor basic-gates

Updated Aug 29, 2023
Verilog

shreegw / Verilog-Projects

FPGA Projects

counter hamming-code lfsr 7-segment-display adder-subtractor booths-multiplier

Updated Jan 19, 2025
Verilog

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