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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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15412e7
[RISCV] Fold vector shift of sext/zext to widening multiply
pfusik Jan 3, 2025
5aa9da4
[RISCV] Fold vector shift to widening multiply on rv32
pfusik Jan 8, 2025
1868507
[RISCV] Use `getSimpleValueType`
pfusik Jan 8, 2025
3a59255
[RISCV] Add a TODO comment
pfusik Jan 8, 2025
174e59e
[RISCV] Handle fixed-length vectors
pfusik Jan 9, 2025
fa18fca
[RISCV] Handle VSEXT_VL/VZEXT_VL
pfusik Jan 10, 2025
0da5f8c
[RISCV] Delay the transform so that vwsll has priority
pfusik Jan 10, 2025
d84396c
[RISCV] Remove dead code handling fixed-length vectors after DAG lega…
pfusik Jan 13, 2025
6df5335
[RISCV] Fix formatting
pfusik Jan 13, 2025
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80 changes: 78 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17341,6 +17341,82 @@ static SDValue combineScalarCTPOPToVCPOP(SDNode *N, SelectionDAG &DAG,
return DAG.getZExtOrTrunc(Pop, DL, VT);
}

static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
const RISCVSubtarget &Subtarget) {
// (shl (zext x), y) -> (vwsll x, y)
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
return V;

// (shl (sext x), C) -> (vwmulsu x, 1u << C)
// (shl (zext x), C) -> (vwmulu x, 1u << C)

if (!DCI.isAfterLegalizeDAG())
return SDValue();

SDValue LHS = N->getOperand(0);
if (!LHS.hasOneUse())
return SDValue();
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For now, this only handles single-use of sext/zext.
I can rewrite it to be part of combineOp_VLToVWOp_VL so that it handles multi-use too.

unsigned Opcode;
switch (LHS.getOpcode()) {
case ISD::SIGN_EXTEND:
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case RISCVISD::VSEXT_VL:
Opcode = RISCVISD::VWMULSU_VL;
break;
case ISD::ZERO_EXTEND:
case RISCVISD::VZEXT_VL:
Opcode = RISCVISD::VWMULU_VL;
break;
default:
return SDValue();
}

SDValue RHS = N->getOperand(1);
APInt ShAmt;
uint64_t ShAmtInt;
if (ISD::isConstantSplatVector(RHS.getNode(), ShAmt))
ShAmtInt = ShAmt.getZExtValue();
else if (RHS.getOpcode() == RISCVISD::VMV_V_X_VL &&
RHS.getOperand(1).getOpcode() == ISD::Constant)
ShAmtInt = RHS.getConstantOperandVal(1);
else
return SDValue();

// Better foldings:
// (shl (sext x), 1) -> (vwadd x, x)
// (shl (zext x), 1) -> (vwaddu x, x)
if (ShAmtInt <= 1)
return SDValue();

SDValue NarrowOp = LHS.getOperand(0);
MVT NarrowVT = NarrowOp.getSimpleValueType();
uint64_t NarrowBits = NarrowVT.getScalarSizeInBits();
if (ShAmtInt >= NarrowBits)
return SDValue();
MVT VT = N->getSimpleValueType(0);
if (NarrowBits * 2 != VT.getScalarSizeInBits())
return SDValue();

SelectionDAG &DAG = DCI.DAG;
SDLoc DL(N);
SDValue Passthru, Mask, VL;
switch (N->getOpcode()) {
case ISD::SHL:
Passthru = DAG.getUNDEF(VT);
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std::tie(Mask, VL) = getDefaultScalableVLOps(VT, DL, DAG, Subtarget);
break;
case RISCVISD::SHL_VL:
Passthru = N->getOperand(2);
Mask = N->getOperand(3);
VL = N->getOperand(4);
break;
default:
llvm_unreachable("Expected SHL");
}
return DAG.getNode(Opcode, DL, VT, NarrowOp,
DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowVT),
Passthru, Mask, VL);
}

SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
Expand Down Expand Up @@ -17970,7 +18046,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
break;
}
case RISCVISD::SHL_VL:
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
if (SDValue V = combineSHL(N, DCI, Subtarget))
return V;
[[fallthrough]];
case RISCVISD::SRA_VL:
Expand All @@ -17995,7 +18071,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SRL:
case ISD::SHL: {
if (N->getOpcode() == ISD::SHL) {
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
if (SDValue V = combineSHL(N, DCI, Subtarget))
return V;
}
SDValue ShAmt = N->getOperand(1);
Expand Down
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