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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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15412e7
[RISCV] Fold vector shift of sext/zext to widening multiply
pfusik Jan 3, 2025
5aa9da4
[RISCV] Fold vector shift to widening multiply on rv32
pfusik Jan 8, 2025
1868507
[RISCV] Use `getSimpleValueType`
pfusik Jan 8, 2025
3a59255
[RISCV] Add a TODO comment
pfusik Jan 8, 2025
174e59e
[RISCV] Handle fixed-length vectors
pfusik Jan 9, 2025
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[RISCV] Fold vector shift of sext/zext to widening multiply 
    (shl (sext X), C) -> (vwmulsu X, 1u << C)
    (shl (zext X), C) -> (vwmulu  X, 1u << C)
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pfusik committed Jan 3, 2025
commit 15412e74bf32e8588dab70427ff178720cbf6c26
76 changes: 74 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17341,6 +17341,78 @@ static SDValue combineScalarCTPOPToVCPOP(SDNode *N, SelectionDAG &DAG,
return DAG.getZExtOrTrunc(Pop, DL, VT);
}

static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
const RISCVSubtarget &Subtarget) {
if (DCI.isBeforeLegalize())
return SDValue();

// (shl (zext x), y) -> (vwsll x, y)
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
return V;

// (shl (sext x), C) -> (vwmulsu x, 1u << C)
// (shl (zext x), C) -> (vwmulu x, 1u << C)

SDValue LHS = N->getOperand(0);
if (!LHS.hasOneUse())
return SDValue();
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For now, this only handles single-use of sext/zext.
I can rewrite it to be part of combineOp_VLToVWOp_VL so that it handles multi-use too.

unsigned Opcode;
switch (LHS.getOpcode()) {
case ISD::SIGN_EXTEND:
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Does it make a difference if we also handle RISCVISD::VSEXT_VL/RISCVISD::VZEXT_VL?

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We probably should, as other widening optimizations do.
There's no rvv test covering this, so I'd need to add one.
How to handle the mask and EVL values? Can this be an operand of ISD::SHL or RISCVISD::SHL_VL or both?

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If you're asking whether VZ/SEXT_VL might appear in RISCVISD::SHL_VL, I think we generate SHL_VL + VZEXT_VL when dealing with some of the interleave vector cases.

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Can SHL_VL have different mask/EVL from its VZ/SEXT_VL operand?

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Can SHL_VL have different mask/EVL from its VZ/SEXT_VL operand?

Technically it's possible

Opcode = RISCVISD::VWMULSU_VL;
break;
case ISD::ZERO_EXTEND:
Opcode = RISCVISD::VWMULU_VL;
break;
default:
return SDValue();
}

SDValue RHS = N->getOperand(1);
APInt ShAmt;
if (!ISD::isConstantSplatVector(RHS.getNode(), ShAmt))
return SDValue();

// Better foldings:
// (shl (sext x), 1) -> (vwadd x, x)
// (shl (zext x), 1) -> (vwaddu x, x)
uint64_t ShAmtInt = ShAmt.getZExtValue();
if (ShAmtInt <= 1)
return SDValue();

SDValue NarrowOp = LHS.getOperand(0);
EVT NarrowVT = NarrowOp.getValueType();
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It's better to use MVT + getSimpleValueType explicitly since this is past type legalization

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Why? I use EVT for DAG.getConstant.

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NarrowVT.getScalarSizeInBits() generates less code if NarrowVT is MVT.

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Done.

uint64_t NarrowBits = NarrowVT.getScalarSizeInBits();
if (ShAmtInt >= NarrowBits)
return SDValue();
EVT VT = N->getValueType(0);
if (NarrowBits * 2 != VT.getScalarSizeInBits())
return SDValue();

SelectionDAG &DAG = DCI.DAG;
SDLoc DL(N);
SDValue Passthru, Mask, VL;
switch (N->getOpcode()) {
case ISD::SHL:
if (!VT.isScalableVector())
return SDValue();
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It might be worthwhile to leave a TODO to handle fixed length vectors later. You would need to use the ContainerVT = getContainerForFixedLengthVector(...) pattern that we use elsewhere.

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TODO added

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Done

Passthru = DAG.getUNDEF(VT);
std::tie(Mask, VL) =
getDefaultScalableVLOps(VT.getSimpleVT(), DL, DAG, Subtarget);
break;
case RISCVISD::SHL_VL:
Passthru = N->getOperand(2);
Mask = N->getOperand(3);
VL = N->getOperand(4);
break;
default:
llvm_unreachable("Expected SHL");
}
return DAG.getNode(Opcode, DL, VT, NarrowOp,
DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowVT),
Passthru, Mask, VL);
}

SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
DAGCombinerInfo &DCI) const {
SelectionDAG &DAG = DCI.DAG;
Expand Down Expand Up @@ -17970,7 +18042,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
break;
}
case RISCVISD::SHL_VL:
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
if (SDValue V = combineSHL(N, DCI, Subtarget))
return V;
[[fallthrough]];
case RISCVISD::SRA_VL:
Expand All @@ -17995,7 +18067,7 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
case ISD::SRL:
case ISD::SHL: {
if (N->getOpcode() == ISD::SHL) {
if (SDValue V = combineOp_VLToVWOp_VL(N, DCI, Subtarget))
if (SDValue V = combineSHL(N, DCI, Subtarget))
return V;
}
SDValue ShAmt = N->getOperand(1);
Expand Down
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