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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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15412e7
[RISCV] Fold vector shift of sext/zext to widening multiply
pfusik Jan 3, 2025
5aa9da4
[RISCV] Fold vector shift to widening multiply on rv32
pfusik Jan 8, 2025
1868507
[RISCV] Use `getSimpleValueType`
pfusik Jan 8, 2025
3a59255
[RISCV] Add a TODO comment
pfusik Jan 8, 2025
174e59e
[RISCV] Handle fixed-length vectors
pfusik Jan 9, 2025
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[RISCV] Fold vector shift to widening multiply on rv32
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@pfusik
pfusik committed Jan 8, 2025
commit 5aa9da4f536c337a8979704aa46c8fc768cabec5
9 changes: 7 additions & 2 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17370,13 +17370,18 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,

SDValue RHS = N->getOperand(1);
APInt ShAmt;
if (!ISD::isConstantSplatVector(RHS.getNode(), ShAmt))
uint64_t ShAmtInt;
if (ISD::isConstantSplatVector(RHS.getNode(), ShAmt))
ShAmtInt = ShAmt.getZExtValue();
else if (RHS.getOpcode() == RISCVISD::VMV_V_X_VL &&
RHS.getOperand(1).getOpcode() == ISD::Constant)
ShAmtInt = RHS.getConstantOperandVal(1);
else
return SDValue();

// Better foldings:
// (shl (sext x), 1) -> (vwadd x, x)
// (shl (zext x), 1) -> (vwaddu x, x)
uint64_t ShAmtInt = ShAmt.getZExtValue();
if (ShAmtInt <= 1)
return SDValue();

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8 changes: 8 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vwsll-sdnode.ll
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Expand Up @@ -222,6 +222,14 @@ define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b
}

define <vscale x 2 x i64> @vwsll_vi_nxv2i64(<vscale x 2 x i32> %a) {
; CHECK-LABEL: vwsll_vi_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a0, 4
; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma
; CHECK-NEXT: vwmulu.vx v10, v8, a0
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64:
; CHECK-ZVBB: # %bb.0:
; CHECK-ZVBB-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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21 changes: 7 additions & 14 deletions llvm/test/CodeGen/RISCV/rvv/vwsll-vp.ll
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Expand Up @@ -238,20 +238,13 @@ define <vscale x 2 x i64> @vwsll_vx_i8_nxv2i64_zext(<vscale x 2 x i32> %a, i8 %b
}

define <vscale x 2 x i64> @vwsll_vi_nxv2i64(<vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i32 zeroext %vl) {
; CHECK-RV32-LABEL: vwsll_vi_nxv2i64:
; CHECK-RV32: # %bb.0:
; CHECK-RV32-NEXT: vsetvli zero, a0, e64, m2, ta, ma
; CHECK-RV32-NEXT: vzext.vf2 v10, v8
; CHECK-RV32-NEXT: vsll.vi v8, v10, 2, v0.t
; CHECK-RV32-NEXT: ret
;
; CHECK-RV64-LABEL: vwsll_vi_nxv2i64:
; CHECK-RV64: # %bb.0:
; CHECK-RV64-NEXT: li a1, 4
; CHECK-RV64-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-RV64-NEXT: vwmulu.vx v10, v8, a1, v0.t
; CHECK-RV64-NEXT: vmv2r.v v8, v10
; CHECK-RV64-NEXT: ret
; CHECK-LABEL: vwsll_vi_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: li a1, 4
; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma
; CHECK-NEXT: vwmulu.vx v10, v8, a1, v0.t
; CHECK-NEXT: vmv2r.v v8, v10
; CHECK-NEXT: ret
;
; CHECK-ZVBB-LABEL: vwsll_vi_nxv2i64:
; CHECK-ZVBB: # %bb.0:
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