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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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[RISCV] Fold vector shift of sext/zext to widening multiply #121563

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15412e7
[RISCV] Fold vector shift of sext/zext to widening multiply
pfusik Jan 3, 2025
5aa9da4
[RISCV] Fold vector shift to widening multiply on rv32
pfusik Jan 8, 2025
1868507
[RISCV] Use `getSimpleValueType`
pfusik Jan 8, 2025
3a59255
[RISCV] Add a TODO comment
pfusik Jan 8, 2025
174e59e
[RISCV] Handle fixed-length vectors
pfusik Jan 9, 2025
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[RISCV] Handle fixed-length vectors
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@pfusik
pfusik committed Jan 9, 2025
commit 174e59e5be1d1c85d2e361551f96e6b542dd38e9
33 changes: 23 additions & 10 deletions llvm/lib/Target/RISCV/RISCVISelLowering.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -17364,6 +17364,9 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
case ISD::ZERO_EXTEND:
Opcode = RISCVISD::VWMULU_VL;
break;
// TODO:
// case RISCVISD::VSEXT_VL:
// case RISCVISD::VZEXT_VL:
default:
return SDValue();
}
Expand All @@ -17386,23 +17389,30 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
return SDValue();

SDValue NarrowOp = LHS.getOperand(0);
uint64_t NarrowBits = NarrowOp.getSimpleValueType().getScalarSizeInBits();
MVT NarrowVT = NarrowOp.getSimpleValueType();
uint64_t NarrowBits = NarrowVT.getScalarSizeInBits();
if (ShAmtInt >= NarrowBits)
return SDValue();
EVT VT = N->getValueType(0);
MVT VT = N->getSimpleValueType(0);
if (NarrowBits * 2 != VT.getScalarSizeInBits())
return SDValue();

SelectionDAG &DAG = DCI.DAG;
MVT NarrowContainerVT = NarrowVT;
MVT ContainerVT = VT;
SDLoc DL(N);
SDValue Passthru, Mask, VL;
switch (N->getOpcode()) {
case ISD::SHL:
if (!VT.isScalableVector())
return SDValue(); // TODO: handle fixed length vectors
if (VT.isFixedLengthVector()) {
NarrowContainerVT =
getContainerForFixedLengthVector(DAG, NarrowVT, Subtarget);
NarrowOp =
convertToScalableVector(NarrowContainerVT, NarrowOp, DAG, Subtarget);
ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
}
Passthru = DAG.getUNDEF(VT);
std::tie(Mask, VL) =
getDefaultScalableVLOps(VT.getSimpleVT(), DL, DAG, Subtarget);
std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
break;
case RISCVISD::SHL_VL:
Passthru = N->getOperand(2);
Expand All @@ -17412,10 +17422,13 @@ static SDValue combineSHL(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
default:
llvm_unreachable("Expected SHL");
}
return DAG.getNode(
Opcode, DL, VT, NarrowOp,
DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), NarrowOp.getValueType()),
Passthru, Mask, VL);
SDValue Mul =
DAG.getNode(Opcode, DL, ContainerVT, NarrowOp,
DAG.getConstant(1ULL << ShAmtInt, SDLoc(RHS), ContainerVT),
Passthru, Mask, VL);
if (VT.isFixedLengthVector())
return convertFromScalableVector(VT, Mul, DAG, Subtarget);
return Mul;
}

SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N,
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