Specifc wire size on AREMPTYSIZE and AWWFULLSIZE parameter #13
Conversation
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I will try to write the simulation test case the describe the issue I encounter asap |
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Here is the test case to reproduce my scenario `include "svut_h.sv"
`timescale 1 ns / 1 ps
module async_fifo_unit_test;
`SVUT_SETUP
`ifndef AEMPTY
`define AEMPTY 1
`endif
`ifndef AFULL
`define AFULL 1
`endif
`ifndef FALLTHROUGH
`define FALLTHROUGH "TRUE"
`endif
parameter DSIZE = 16;
parameter ASIZE = 13;
parameter AREMPTYSIZE = `AEMPTY;
parameter AWFULLSIZE = 4096;
parameter FALLTHROUGH = `FALLTHROUGH;
parameter MAX_TRAFFIC = 10;
integer timeout;
reg wclk;
reg wrst_n;
reg winc;
reg [DSIZE-1:0] wdata;
wire wfull;
wire awfull;
reg rclk;
reg rrst_n;
reg rinc;
wire [DSIZE-1:0] rdata;
wire rempty;
wire arempty;
async_fifo
#(
.DSIZE (DSIZE),
.ASIZE (ASIZE),
.AWFULLSIZE (AWFULLSIZE),
.AREMPTYSIZE (AREMPTYSIZE),
.FALLTHROUGH (FALLTHROUGH)
)
dut
(
wclk,
wrst_n,
winc,
wdata,
wfull,
awfull,
rclk,
rrst_n,
rinc,
rdata,
rempty,
arempty
);
// An example to create a clock
initial wclk = 1'b0;
always #2 wclk <= ~wclk;
initial rclk = 1'b0;
always #3 rclk <= ~rclk;
// An example to dump data for visualization
initial begin
$dumpfile("async_fifo_unit_test.vcd");
$dumpvars(0, async_fifo_unit_test);
end
task setup(msg="Setup testcase");
begin
wrst_n = 1'b0;
winc = 1'b0;
wdata = 0;
rrst_n = 1'b0;
rinc = 1'b0;
#100;
wrst_n = 1;
rrst_n = 1;
#50;
timeout = 0;
@(posedge wclk);
end
endtask
task teardown(msg="Tearing down");
begin
#50;
end
endtask
`TEST_SUITE("ASYNCFIFO")
`UNIT_TEST("TEST_IDLE")
`FAIL_IF(wfull);
`FAIL_IF(!rempty);
`UNIT_TEST_END
`UNIT_TEST("TEST_MULTIPLE_WRITE_THEN_READ")
// repeat for 3 times
for( int j = 0; j < 3; j= j+1)begin
// write 4096 data
winc = 1;
for (int i=0; i<(2**(ASIZE-1)); i=i+1) begin
@(negedge wclk)
wdata = i;
end
@(negedge wclk);
winc = 0;
@(posedge wclk)
`FAIL_IF_NOT_EQUAL(awfull, 1);
// try to read it
@(posedge rclk);
rinc = 1;
for (int i=0; i<(2**(ASIZE-1)); i=i+1) begin
@(posedge rclk);
`FAIL_IF_NOT_EQUAL(rdata, i);
end
@(negedge rclk);
rinc = 0;
`FAIL_IF(rempty == 0);
end
`UNIT_TEST_END
`TEST_SUITE_END
endmodule |
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The simulation also fails the testcase if I don't specify the wire size for the parameter as follows parameter [ADDRSIZE:0]AREMPTYSIZE = 1 |
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Very good! I'll spend some times to double check tomorrow and merge it. Damien |
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Hi, I merged the branch in my master and added the test case in my test bench but it fails. Did I do a mistake or is it still failing with the parameter size specified? |
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ok forget my last comment, I saw you tricked the test bench, my bad... Anyway, is everything is OK with your last update now? |
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Actually, I am sorry that I have to confess that I made a mistake in my testing. Please forgive me for that. I think what happened is that I accidentally run my test cases on my cast-parameter involved in using old method The cast-parameter passed the testcase. But just now when I rerun the testcase on fix-parameter-branch, the branch that got merged, it failed the test case. Thus, it look like the proposed fixe did not work as expected. Probably what happened is that I forget to change branch when I run the test case. I am so sorry for my mistake :( The output from the branch that actually pass the test case. Sorry once again! shouyu@shouyu-LOQ-15APH8:~/async_fifo$ ./flow.sh sim
INFO: Start Aync FIFO Flow
script/setup.sh: line 12: type: svutRun: not found
INFO: Enable SVUT in PATH
INFO: Start simulation
______ ____ ________
/ ___/ | / / / / /_ __/
\__ \| | / / / / / / /
___/ /| |/ / /_/ / / /
/____/ |___/\____/ /_/
v1.9.0
SVUT (@ 18:10:36) Run with Icarus Verilog
SVUT (@ 18:10:36) Start async_fifo_unit_test.sv
SVUT (@ 18:10:36) iverilog -g2012 -Wall -o svut.out -f files.f async_fifo_unit_test.sv
warning: Some design elements have no explicit time unit and/or
: time precision. This may cause confusing timing results.
: Affected design elements are:
: -- compilation unit
SVUT (@ 18:10:37) vvp svut.out
VCD info: dumpfile async_fifo_unit_test.vcd opened for output.
INFO: Start testsuite << ASYNCFIFO >> (@ 0)
INFO: Starting << Test 0: TEST_IDLE >> (@ 0)
SUCCESS: Test 0 pass (@ 200000)
INFO: Starting << Test 1: TEST_MULTIPLE_WRITE_THEN_READ >> (@ 200000)
SUCCESS: Test 1 pass (@ 123308000)
INFO: Stop testsuite 'ASYNCFIFO' (@ 123308000)
- Warning number: 0
- Critical number: 0
- Error number: 0
- STATUS: 2/2 test(s) passed
async_fifo_unit_test.sv:176: $finish called at 123308000 (1ps)
SVUT (@ 18:10:37) Stop async_fifo_unit_test.sv
SVUT (@ 18:10:37) Elapsed time: 0:00:00.245708
shouyu@shouyu-LOQ-15APH8:~/async_fifo$ git branch -a
* (HEAD detached at origin/cast-parameter)
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Do you want to roll-back the merge and I create a new PR from the branch that actually runs correctly? Sorry once again :( @dpretet |
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No problem, everybody does mistakes buddy :) I think I will be conservative about this update and roll-back the master with the previous version (v1.2.0, before the almost threshold setup). I'd like you do a new merge request with all your updates (systemverilog casting style) on the branch aflags which is aligned with your last pull request. I'll try to do more extensive tests about this feature in simulation. I'd like also you take time to test your update on hardware while you looks to have a good platform to check it and give me a feedback later. I'll merge again this feature which I think is a nice-to-have and will probably convert the whole code in systemverilog, so simplify this tricky casting thing. Best, |
See issue: #12