Description
I haven't tried to produce this in simulation yet. I will try to do it when I am free
During testing and usage, I found something interesting.
ASIZE = 13, DSIZE = 16,AWFULLSIZE = 4096 // half of the buffer
To test the correctness of my FIFO logic, I have my FPGA setup to be in a FIFO stream-in-out testing mode.
The Verilog will first read 4096 DSIZE data from the FIFO interface provided by Cypress FX3 and then write the data back to the host laptop.
After the 4096 DSIZE read, I assert the awful flag, which should be true since I am at half of the FIFO and AWFULLSIZE == 4096.
If Awfull is true, I will move to the next state to write the data back to the host laptop. But if awfull is not true, the FPGA will enter into an error state.
At the actual testing, the awfull flag is asserted to be true at the first 2 iterations of 4096 fifo read & write. However, at the 3 iteration, the assertion statement failed!
After looking over the document of the async fifo implementation and comparing the changes that I made from the last merge, I realized the problem is AWFULLSIZE is not being bit width cast.
I was able to fix the issue of inconsistent awfull signal by making the modification to cast the parameter into wires of (ADDRESIZE+1), same size with wgraynext.
Note: after making the changes, it still passes the simulation test.