Feature: Add Threshold for almost flag

[joeldushouyu]

Instead of doing the SystemVerilog trick that I described earlier, I define one more addition registers wbinnextpt1, similar for rpt_empty.

Thus, I believe the code could still be keep in Verilog instead of rewritten in systemverilog, as mentioned in the previous comment in #13 (comment)

Moreover, I have tested in

1. Physical hardware
2. Simulation, I have added a new ,sv testfile that replicated the scenario where I find the issue. I am not sure if you want to merge the test case into the main test case.

Once again, thank you very much for your patience! I am so sorry about the mistake that I made earlier :(

[joeldushouyu]

The output of current test case is

shouyu@shouyu-LOQ-15APH8:~/async_fifo$ ./flow.sh sim

INFO: Start Aync FIFO Flow
script/setup.sh: line 12: type: svutRun: not found
INFO: Enable SVUT in PATH
INFO: Start simulation

       ______    ____  ________
      / ___/ |  / / / / /_  __/
      \__ \| | / / / / / / /  
     ___/ /| |/ / /_/ / / /   
    /____/ |___/\____/ /_/

    v1.9.0

SVUT (@ 01:04:07) Run with Icarus Verilog

SVUT (@ 01:04:07) Start async_fifo_unit_test.sv

SVUT (@ 01:04:07) iverilog -g2012 -Wall -o svut.out -f files.f  async_fifo_unit_test.sv 

warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- compilation unit
SVUT (@ 01:04:07) vvp svut.out 

VCD info: dumpfile async_fifo_unit_test.vcd opened for output.

INFO: Start testsuite << ASYNCFIFO >> (@ 0)

INFO: Starting << Test 0: TEST_IDLE >> (@ 0)
SUCCESS: Test 0 pass (@ 200000)

INFO: Starting << Test 1: TEST_SINGLE_WRITE_THEN_READ >> (@ 200000)
SUCCESS: Test 1 pass (@ 428000)

INFO: Starting << Test 2: TEST_MULTIPLE_WRITE_THEN_READ >> (@ 428000)
SUCCESS: Test 2 pass (@ 833000)

INFO: Starting << Test 3: TEST_FULL_FLAG >> (@ 833000)
SUCCESS: Test 3 pass (@ 1104000)

INFO: Starting << Test 4: TEST_EMPTY_FLAG >> (@ 1104000)
SUCCESS: Test 4 pass (@ 1368000)

INFO: Starting << Test 5: TEST_ALMOST_EMPTY_FLAG >> (@ 1368000)
SUCCESS: Test 5 pass (@ 1674000)

INFO: Starting << Test 6: TEST_ALMOST_FULL_FLAG >> (@ 1674000)
SUCCESS: Test 6 pass (@ 1940000)

INFO: Starting << Test 7: TEST_CONCURRENT_WRITE_READ >> (@ 1940000)
SUCCESS: Test 7 pass (@ 2222000)

INFO: Stop testsuite 'ASYNCFIFO' (@ 2222000)
  - Warning number:  0
  - Critical number: 0
  - Error number:    0
  - STATUS: 8/8 test(s) passed

async_fifo_unit_test.sv:288: $finish called at 2222000 (1ps)
SVUT (@ 01:04:07) Stop async_fifo_unit_test.sv

SVUT (@ 01:04:07) Elapsed time: 0:00:00.030571



       ______    ____  ________
      / ___/ |  / / / / /_  __/
      \__ \| | / / / / / / /  
     ___/ /| |/ / /_/ / / /   
    /____/ |___/\____/ /_/

    v1.9.0

SVUT (@ 01:04:07) Run with Icarus Verilog

SVUT (@ 01:04:07) Start async_fifo_almost_threshold_test.sv

SVUT (@ 01:04:07) iverilog -g2012 -Wall -o svut.out -f files.f  async_fifo_almost_threshold_test.sv 

warning: Some design elements have no explicit time unit and/or
       : time precision. This may cause confusing timing results.
       : Affected design elements are:
       :   -- compilation unit
SVUT (@ 01:04:07) vvp svut.out 

VCD info: dumpfile async_fifo_unit_test.vcd opened for output.

INFO: Start testsuite << ASYNCFIFO >> (@ 0)

INFO: Starting << Test 0: TEST_IDLE >> (@ 0)
SUCCESS: Test 0 pass (@ 200000)

INFO: Starting << Test 1: TEST_MULTIPLE_WRITE_THEN_READ >> (@ 200000)
SUCCESS: Test 1 pass (@ 123308000)

INFO: Stop testsuite 'ASYNCFIFO' (@ 123308000)
  - Warning number:  0
  - Critical number: 0
  - Error number:    0
  - STATUS: 2/2 test(s) passed

async_fifo_almost_threshold_test.sv:176: $finish called at 123308000 (1ps)
SVUT (@ 01:04:07) Stop async_fifo_almost_threshold_test.sv

SVUT (@ 01:04:07) Elapsed time: 0:00:00.252861

[dpretet]

Hello,

thank you for the pull request. I’ll merge it when I’ll got some times in the next weeks.

Best,
Damien

[joeldushouyu]

Just checking, no hurries. Any update on the review progress?

By the way if you are interested to see how I use this project to my undergraduate senior project: https://github.com/joeldushouyu/ExternalGraphicCard

[dpretet]

Hello 👋 Thanks for sharing the project, it’s always interesting to see user applications ☺️Not advance yet, I’m working on another projects nowadays. I hope to find time next month, I will be on vacation so I’ll got time to convert the full code to system verilog and merge your pull request. Sorry for the delay. Best,DamienLe 27 mai 2024 à 22:26, Shouyu ***@***.***> a écrit : Just checking, no hurries. Any update on the review progress? By the way if you are interested to see how I use this project to my undergraduate senior project: https://github.com/joeldushouyu/ExternalGraphicCard —Reply to this email directly, view it on GitHub, or unsubscribe.You are receiving this because you commented.Message ID: ***@***.***>

[joeldushouyu]

Hello 👋 Thanks for sharing the project, it’s always interesting to see user applications ☺️Not advance yet, I’m working on another projects nowadays. I hope to find time next month, I will be on vacation so I’ll got time to convert the full code to system verilog and merge your pull request. Sorry for the delay. Best,DamienLe 27 mai 2024 à 22:26, Shouyu @.> a écrit : Just checking, no hurries. Any update on the review progress? By the way if you are interested to see how I use this project to my undergraduate senior project: https://github.com/joeldushouyu/ExternalGraphicCard —Reply to this email directly, view it on GitHub, or unsubscribe.You are receiving this because you commented.Message ID: @.>

Thanks for the update and the comment!
Just a comment on the Systemverilog idea. In this merge, I did not use the "Casting-method" that I used last time. Rather, I define two more additional registers (see the merge request for detail). Thus, I think it might actually be okay if keep the code in Verilog. While, I could be totally wrong though. 😏