JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C
#98332
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ghost
added
the
area-CodeGen-coreclr
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch Issue DetailsContributes to #94549 Adds formats:
Left: Capstone,
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TIHan
changed the title
SVE_HX_3A_B to SVE_JL_3A' and SVE_IC_3A to SVE_IC_3A_C`SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C
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@dotnet/jit-contrib @dotnet/arm64-contrib @kunalspathak @a74nh this is ready. |
Diff results for #98332Throughput diffsThroughput diffs for linux/arm64 ran on windows/x64Overall (+0.04% to +0.08%)
MinOpts (+0.06% to +0.18%)
FullOpts (+0.04% to +0.08%)
Throughput diffs for osx/arm64 ran on windows/x64Overall (+0.04% to +0.08%)
MinOpts (+0.06% to +0.15%)
FullOpts (+0.03% to +0.08%)
Throughput diffs for windows/arm64 ran on windows/x64Overall (+0.04% to +0.08%)
MinOpts (+0.07% to +0.18%)
FullOpts (+0.04% to +0.08%)
Details here Throughput diffs for linux/arm64 ran on linux/x64MinOpts (-0.00% to +0.01%)
Details here |
a74nh
reviewed
Feb 13, 2024
amanasifkhalid
approved these changes
Feb 15, 2024
src/coreclr/jit/emitarm64.cpp
Outdated
| * | ||
| * Prints the encoding for format [<Zn>.D{, #<imm>}] | ||
| */ | ||
| void emitter::emitDispSveImmIndex(regNumber reg1, insOpts opt, ssize_t imm) |
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Can this logic be merged into emitDispSveImm in #98468 (or the other way around)?
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It doesn't matter either way. I'll have to resolve any conflicts when my PRs get merged, and that will include some cleanup.
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Also do you know where the TP impact is coming from on Windows x64? Your changes look like they only affect SVE paths. |
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It's probably just the additional cases in emitIns. Should split it out to see if the TP regressions clear up. |
Diff results for #98332Throughput diffsThroughput diffs for linux/arm64 ran on windows/x64MinOpts (-0.00% to +0.01%)
Throughput diffs for osx/arm64 ran on windows/x64MinOpts (-0.01% to +0.01%)
Details here |
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Merging, failures are not related. |
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Contributes to #94549
Adds formats:
Left: Capstone,
Right: Jit