Arm64: Implement SVE encodings

[kunalspathak]

Summary

Based upon the model I prototyped in #94529, let us try to use the boilerplate code that the tool generated to implement following methods.

• emitArm64EmitterUnitTests_sve.cpp.txt
• emitDispInsHelp_sve.cpp.txt
• emitInsSanityCheck_sve.cpp.txt
• emitPerfScore_sve.cpp.txt
• emitOutputInstr_sve.cpp.txt

Code needed in various emitIns_* methods:

• emitIns_R_I_sve.cpp.txt
• emitIns_R_R_I_sve.cpp.txt
• emitIns_R_R_R_I_sve.cpp.txt
• emitIns_R_R_R_R_I_sve.cpp.txt
• emitIns_R_R_R_R_sve.cpp.txt
• emitIns_R_R_R_sve.cpp.txt
• emitIns_R_R_sve.cpp.txt
• emitIns_R_sve.cpp.txt
• emitIns_TODO_sve.cpp.txt

I have split the implementation among Alan, Aman and Will. I will join the efforts once I get am done with register allocation support for predicate registers. Once I do some cleanup to the tool, I will share the repo of the tool so you can generate the boiler plate files on your own.

PR expectation

Start sequentially with the format names that are assigned and send PRs. In the PR, it will be useful to paste the disassembly produced from instructions in #94549 (comment). The expectation is to have the encoding validated before submitting the PR.

References

• https://dougallj.github.io/asil/index.html
• https://docsmirror.github.io/A64/2023-06/sveindex.html
• https://developer.arm.com/downloads/-/exploration-tools
• https://github.com/llvm/llvm-project/tree/ea991a11b2a3d2bfa545adbefb71cd17e8970a43/llvm/test/MC/AArch64
• Here is the hierarchy of all the instruction format pattern, format names and instruction's asm syntax. They are arranged in following order:
• Instruction Pattern
  • Instruction Format 1
    • Instr1 Asm syntax
    • Instr2 Asm syntax
  • Instruction Format 2
  • ...

List of format patterns

..........iiiiii ...iiinnnnn.TTTT

SVE_ID_2A

LDR     <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_JG_2A

STR     <Pt>, [<Xn|SP>{, #<imm>, MUL VL}]d

..........iiiiii ...iiinnnnnttttt

SVE_IE_2A

LDR     <Zt>, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_JH_2A

STR     <Zt>, [<Xn|SP>{, #<imm>, MUL VL}]

........xx...... ...gggmmmmmddddd

SVE_AA_3A

AND     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
BIC     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
EOR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
ORR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_AB_3A

ADD     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SUB     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SUBR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_AC_3A

SDIV    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SDIVR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UDIV    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UDIVR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_AD_3A

SABD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UABD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_AE_3A

MUL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SMULH   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UMULH   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_AN_3A

ASR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
ASRR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
LSL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
LSLR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
LSR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
LSRR    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_AO_3A

ASR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
LSL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D
LSR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.D

SVE_CM_3A

CLASTA  <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>
CLASTB  <Zdn>.<T>, <Pg>, <Zdn>.<T>, <Zm>.<T>

SVE_CN_3A

CLASTA  <V><dn>, <Pg>, <V><dn>, <Zm>.<T>
CLASTB  <V><dn>, <Pg>, <V><dn>, <Zm>.<T>

SVE_CO_3A

CLASTA  <R><dn>, <Pg>, <R><dn>, <Zm>.<T>
CLASTB  <R><dn>, <Pg>, <R><dn>, <Zm>.<T>

SVE_EP_3A

SHADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SHSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SHSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SRHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UHADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UHSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UHSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
URHADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_ER_3A

ADDP    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SMAXP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SMINP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UMAXP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UMINP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_ET_3A

SQADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SQSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SQSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SUQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UQADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UQSUB   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UQSUBR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
USQADD  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_EU_3A

SQRSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SQRSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SQSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SRSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
SRSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UQRSHL  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UQRSHLR <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
UQSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
URSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
URSHLR  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_GR_3A

FADDP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMAXNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMAXP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMINNMP <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMINP   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

SVE_HJ_3A

FADDA   <V><dn>, <Pg>, <V><dn>, <Zm>.<T>

SVE_HL_3A

FABD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FADD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FAMAX   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FAMIN   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FDIV    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FDIVR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMAXNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMINNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMUL    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FMULX   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FSCALE  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FSUB    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>
FSUBR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>

........xx.mmmmm ......nnnnnddddd

SVE_AT_3A

ADD     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
SQADD   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
SQSUB   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
SUB     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
UQADD   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
UQSUB   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_BA_3A

INDEX   <Zd>.<T>, <R><n>, <R><m>

SVE_BD_3A

MUL     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
SMULH   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
UMULH   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_BE_3A

SQDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
SQRDMULH <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_BG_3A

ASR     <Zd>.<T>, <Zn>.<T>, <Zm>.D
LSL     <Zd>.<T>, <Zn>.<T>, <Zm>.D
LSR     <Zd>.<T>, <Zn>.<T>, <Zm>.D

SVE_BK_3A

FTSSEL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_BR_3A

TRN1    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
TRN2    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
UZP1    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
UZP2    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
ZIP1    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
ZIP2    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_BZ_3A

TBL     <Zd>.<T>, {<Zn>.<T>}, <Zm>.<T>
TBX     <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_BZ_3A_A

TBL     <Zd>.<T>, {<Zn1>.<T>, <Zn2>.<T>}, <Zm>.<T>

SVE_CA_3A

TBXQ    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_EH_3A

SDOT    <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UDOT    <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_EL_3A

SMLALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SMLALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SMLSLB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SMLSLT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UMLALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UMLALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UMLSLB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UMLSLT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_EM_3A

SQRDMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
SQRDMLSH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_EN_3A

SQDMLALBT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SQDMLSLBT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_EO_3A

SQDMLALB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SQDMLALT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SQDMLSLB <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SQDMLSLT <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_EV_3A

SCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
UCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_EX_3A

TBLQ    <Zd>.<T>, {<Zn>.<T>}, <Zm>.<T>
UZPQ1   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
UZPQ2   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
ZIPQ1   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
ZIPQ2   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_FL_3A

SABDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SABDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SADDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SADDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SSUBLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SSUBLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UABDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UABDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UADDLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UADDLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
USUBLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
USUBLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_FM_3A

SADDWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
SADDWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
SSUBWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
SSUBWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
UADDWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
UADDWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
USUBWB  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>
USUBWT  <Zd>.<T>, <Zn>.<T>, <Zm>.<Tb>

SVE_FN_3A

PMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
PMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SQDMULLB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SQDMULLT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UMULLB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UMULLT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_FP_3A

EORBT   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
EORTB   <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_FQ_3A

BDEP    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
BEXT    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
BGRP    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_FS_3A

SADDLBT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SSUBLBT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SSUBLTB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_FW_3A

SABA    <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
UABA    <Zda>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_FX_3A

SABALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SABALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UABALB  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
UABALT  <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_GC_3A

ADDHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
ADDHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
RADDHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
RADDHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
RSUBHNB <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
RSUBHNT <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SUBHNB  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>
SUBHNT  <Zd>.<T>, <Zn>.<Tb>, <Zm>.<Tb>

SVE_GF_3A

HISTSEG <Zd>.B, <Zn>.B, <Zm>.B

SVE_GW_3A

FCLAMP  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

SVE_HK_3A

FADD    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
FMUL    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
FRECPS  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
FRSQRTS <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
FSUB    <Zd>.<T>, <Zn>.<T>, <Zm>.<T>
FTSMUL  <Zd>.<T>, <Zn>.<T>, <Zm>.<T>

........xx...... ..hiiiiiiiiddddd

SVE_EB_1A

DUP     <Zd>.<T>, #<imm>{, <shift>}
MOV     <Zd>.<T>, #<imm>{, <shift>}

SVE_EC_1A

ADD     <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
SQADD   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
SQSUB   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
SUB     <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
SUBR    <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
UQADD   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}
UQSUB   <Zdn>.<T>, <Zdn>.<T>, #<imm>{, <shift>}

...........mmmmm ......nnnnnddddd

SVE_AT_3B

ADDPT   <Zd>.D, <Zn>.D, <Zm>.D
SUBPT   <Zd>.D, <Zn>.D, <Zm>.D

SVE_AU_3A

AND     <Zd>.D, <Zn>.D, <Zm>.D
BIC     <Zd>.D, <Zn>.D, <Zm>.D
EOR     <Zd>.D, <Zn>.D, <Zm>.D
MOV     <Zd>.D, <Zn>.D
ORR     <Zd>.D, <Zn>.D, <Zm>.D

SVE_BD_3B

PMUL    <Zd>.B, <Zn>.B, <Zm>.B

SVE_BR_3B

TRN1    <Zd>.Q, <Zn>.Q, <Zm>.Q
TRN2    <Zd>.Q, <Zn>.Q, <Zm>.Q
UZP1    <Zd>.Q, <Zn>.Q, <Zm>.Q
UZP2    <Zd>.Q, <Zn>.Q, <Zm>.Q
ZIP1    <Zd>.Q, <Zn>.Q, <Zm>.Q
ZIP2    <Zd>.Q, <Zn>.Q, <Zm>.Q

SVE_EF_3A

SDOT    <Zda>.S, <Zn>.H, <Zm>.H
UDOT    <Zda>.S, <Zn>.H, <Zm>.H

SVE_EI_3A

USDOT   <Zda>.S, <Zn>.B, <Zm>.B

SVE_EW_3A

MLAPT   <Zda>.D, <Zn>.D, <Zm>.D

SVE_FN_3B

PMULLB  <Zd>.Q, <Zn>.D, <Zm>.D
PMULLT  <Zd>.Q, <Zn>.D, <Zm>.D

SVE_FO_3A

SMMLA   <Zda>.S, <Zn>.B, <Zm>.B
UMMLA   <Zda>.S, <Zn>.B, <Zm>.B
USMMLA  <Zda>.S, <Zn>.B, <Zm>.B

SVE_GJ_3A

RAX1    <Zd>.D, <Zn>.D, <Zm>.D
SM4EKEY <Zd>.S, <Zn>.S, <Zm>.S

SVE_GN_3A

FMLALB  <Zda>.H, <Zn>.B, <Zm>.B
FMLALT  <Zda>.H, <Zn>.B, <Zm>.B

SVE_GO_3A

FMLALLBB <Zda>.S, <Zn>.B, <Zm>.B
FMLALLBT <Zda>.S, <Zn>.B, <Zm>.B
FMLALLTB <Zda>.S, <Zn>.B, <Zm>.B
FMLALLTT <Zda>.S, <Zn>.B, <Zm>.B

SVE_GW_3B

BFCLAMP <Zd>.H, <Zn>.H, <Zm>.H

SVE_HA_3A

BFDOT   <Zda>.S, <Zn>.H, <Zm>.H
FDOT    <Zda>.S, <Zn>.H, <Zm>.H

SVE_HA_3A_E

FDOT    <Zda>.H, <Zn>.B, <Zm>.B

SVE_HA_3A_F

FDOT    <Zda>.S, <Zn>.B, <Zm>.B

SVE_HB_3A

BFMLALB <Zda>.S, <Zn>.H, <Zm>.H
BFMLALT <Zda>.S, <Zn>.H, <Zm>.H
BFMLSLB <Zda>.S, <Zn>.H, <Zm>.H
BFMLSLT <Zda>.S, <Zn>.H, <Zm>.H
FMLALB  <Zda>.S, <Zn>.H, <Zm>.H
FMLALT  <Zda>.S, <Zn>.H, <Zm>.H
FMLSLB  <Zda>.S, <Zn>.H, <Zm>.H
FMLSLT  <Zda>.S, <Zn>.H, <Zm>.H

SVE_HD_3A

BFMMLA  <Zda>.S, <Zn>.H, <Zm>.H

SVE_HD_3A_A

FMMLA   <Zda>.D, <Zn>.D, <Zm>.D

SVE_HK_3B

BFADD   <Zd>.H, <Zn>.H, <Zm>.H
BFMUL   <Zd>.H, <Zn>.H, <Zm>.H
BFSUB   <Zd>.H, <Zn>.H, <Zm>.H

..............ii iiiiiiiiiiiddddd

SVE_BS_1A

AND     <Zdn>.<T>, <Zdn>.<T>, #<const>
BIC     <Zdn>.<T>, <Zdn>.<T>, #<const>
EON     <Zdn>.<T>, <Zdn>.<T>, #<const>
EOR     <Zdn>.<T>, <Zdn>.<T>, #<const>
ORN     <Zdn>.<T>, <Zdn>.<T>, #<const>
ORR     <Zdn>.<T>, <Zdn>.<T>, #<const>

SVE_BT_1A

DUPM    <Zd>.<T>, #<const>
MOV     <Zd>.<T>, #<const>

........xx..gggg ..hiiiiiiiiddddd

SVE_BV_2A

CPY     <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>}
MOV     <Zd>.<T>, <Pg>/Z, #<imm>{, <shift>}

SVE_BV_2A_A

CPY     <Zd>.<T>, <Pg>/M, #<imm>{, <shift>}

SVE_BV_2A_J

MOV     <Zd>.<T>, <Pg>/M, #<imm>{, <shift>}

........ii.xxxxx ......nnnnnddddd

SVE_BW_2A

DUP     <Zd>.<T>, <Zn>.<T>[<imm>]
MOV     <Zd>.<T>, <Zn>.<T>[<imm>]

........xx...... ......nnnnnddddd

SVE_BJ_2A

FEXPA   <Zd>.<T>, <Zn>.<T>

SVE_CB_2A

DUP     <Zd>.<T>, <R><n|SP>
MOV     <Zd>.<T>, <R><n|SP>

SVE_CG_2A

REV     <Zd>.<T>, <Zn>.<T>

SVE_CH_2A

SUNPKHI <Zd>.<T>, <Zn>.<Tb>
SUNPKLO <Zd>.<T>, <Zn>.<Tb>
UUNPKHI <Zd>.<T>, <Zn>.<Tb>
UUNPKLO <Zd>.<T>, <Zn>.<Tb>

SVE_HF_2A

FRECPE  <Zd>.<T>, <Zn>.<T>
FRSQRTE <Zd>.<T>, <Zn>.<T>

........xx...... ...gggnnnnnddddd

SVE_AF_3A

ANDV    <V><d>, <Pg>, <Zn>.<T>
EORV    <V><d>, <Pg>, <Zn>.<T>
ORV     <V><d>, <Pg>, <Zn>.<T>

SVE_AG_3A

ANDQV   <Vd>.<T>, <Pg>, <Zn>.<Tb>
EORQV   <Vd>.<T>, <Pg>, <Zn>.<Tb>
ORQV    <Vd>.<T>, <Pg>, <Zn>.<Tb>

SVE_AI_3A

SADDV   <Dd>, <Pg>, <Zn>.<T>
UADDV   <Dd>, <Pg>, <Zn>.<T>

SVE_AJ_3A

ADDQV   <Vd>.<T>, <Pg>, <Zn>.<Tb>

SVE_AK_3A

SMAXV   <V><d>, <Pg>, <Zn>.<T>
SMINV   <V><d>, <Pg>, <Zn>.<T>
UMAXV   <V><d>, <Pg>, <Zn>.<T>
UMINV   <V><d>, <Pg>, <Zn>.<T>

SVE_AL_3A

SMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
SMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
UMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
UMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>

SVE_AP_3A

CLS     <Zd>.<T>, <Pg>/M, <Zn>.<T>
CLZ     <Zd>.<T>, <Pg>/M, <Zn>.<T>
CNOT    <Zd>.<T>, <Pg>/M, <Zn>.<T>
CNT     <Zd>.<T>, <Pg>/M, <Zn>.<T>
FABS    <Zd>.<T>, <Pg>/M, <Zn>.<T>
FNEG    <Zd>.<T>, <Pg>/M, <Zn>.<T>
NOT     <Zd>.<T>, <Pg>/M, <Zn>.<T>

SVE_AQ_3A

ABS     <Zd>.<T>, <Pg>/M, <Zn>.<T>
NEG     <Zd>.<T>, <Pg>/M, <Zn>.<T>
SXTB    <Zd>.<T>, <Pg>/M, <Zn>.<T>
SXTH    <Zd>.<T>, <Pg>/M, <Zn>.<T>
SXTW    <Zd>.D, <Pg>/M, <Zn>.D
UXTB    <Zd>.<T>, <Pg>/M, <Zn>.<T>
UXTH    <Zd>.<T>, <Pg>/M, <Zn>.<T>
UXTW    <Zd>.D, <Pg>/M, <Zn>.D

SVE_CL_3A

COMPACT <Zd>.<T>, <Pg>, <Zn>.<T>

SVE_CP_3A

CPY     <Zd>.<T>, <Pg>/M, <V><n>
MOV     <Zd>.<T>, <Pg>/M, <V><n>

SVE_CQ_3A

CPY     <Zd>.<T>, <Pg>/M, <R><n|SP>
MOV     <Zd>.<T>, <Pg>/M, <R><n|SP>

SVE_CR_3A

LASTA   <V><d>, <Pg>, <Zn>.<T>
LASTB   <V><d>, <Pg>, <Zn>.<T>

SVE_CS_3A

LASTA   <R><d>, <Pg>, <Zn>.<T>
LASTB   <R><d>, <Pg>, <Zn>.<T>

SVE_CU_3A

RBIT    <Zd>.<T>, <Pg>/M, <Zn>.<T>
REVB    <Zd>.<T>, <Pg>/M, <Zn>.<T>
REVH    <Zd>.<T>, <Pg>/M, <Zn>.<T>
REVW    <Zd>.D, <Pg>/M, <Zn>.D

SVE_EQ_3A

SADALP  <Zda>.<T>, <Pg>/M, <Zn>.<Tb>
UADALP  <Zda>.<T>, <Pg>/M, <Zn>.<Tb>

SVE_ES_3A

SQABS   <Zd>.<T>, <Pg>/M, <Zn>.<T>
SQNEG   <Zd>.<T>, <Pg>/M, <Zn>.<T>
URECPE  <Zd>.S, <Pg>/M, <Zn>.S
URSQRTE <Zd>.S, <Pg>/M, <Zn>.S

SVE_GS_3A

FADDQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
FMAXNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
FMAXQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>
FMINNMQV <Vd>.<T>, <Pg>, <Zn>.<Tb>
FMINQV  <Vd>.<T>, <Pg>, <Zn>.<Tb>

SVE_HE_3A

FADDV   <V><d>, <Pg>, <Zn>.<T>
FMAXNMV <V><d>, <Pg>, <Zn>.<T>
FMAXV   <V><d>, <Pg>, <Zn>.<T>
FMINNMV <V><d>, <Pg>, <Zn>.<T>
FMINV   <V><d>, <Pg>, <Zn>.<T>

SVE_HQ_3A

FRINTA  <Zd>.<T>, <Pg>/M, <Zn>.<T>
FRINTI  <Zd>.<T>, <Pg>/M, <Zn>.<T>
FRINTM  <Zd>.<T>, <Pg>/M, <Zn>.<T>
FRINTN  <Zd>.<T>, <Pg>/M, <Zn>.<T>
FRINTP  <Zd>.<T>, <Pg>/M, <Zn>.<T>
FRINTX  <Zd>.<T>, <Pg>/M, <Zn>.<T>
FRINTZ  <Zd>.<T>, <Pg>/M, <Zn>.<T>

SVE_HR_3A

FRECPX  <Zd>.<T>, <Pg>/M, <Zn>.<T>
FSQRT   <Zd>.<T>, <Pg>/M, <Zn>.<T>

........xx.mmmmm ..VVVVnnnnnddddd

SVE_CW_4A

MOV     <Zd>.<T>, <Pv>/M, <Zn>.<T>
SEL     <Zd>.<T>, <Pv>, <Zn>.<T>, <Zm>.<T>

............MMMM ..gggg.NNNN.DDDD

SVE_CZ_4A

AND     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
ANDS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
BIC     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
BICS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
EOR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
EORS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
MOV     <Pd>.B, <Pg>/Z, <Pn>.B
MOVS    <Pd>.B, <Pg>/Z, <Pn>.B
NAND    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NANDS   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NOR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NORS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
NOT     <Pd>.B, <Pg>/Z, <Pn>.B
NOTS    <Pd>.B, <Pg>/Z, <Pn>.B
ORN     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
ORNS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
ORR     <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
ORRS    <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
SEL     <Pd>.B, <Pg>, <Pn>.B, <Pm>.B

SVE_CZ_4A_A

MOVS    <Pd>.B, <Pn>.B

SVE_CZ_4A_K

MOV     <Pd>.B, <Pg>/M, <Pn>.B

SVE_CZ_4A_L

MOV     <Pd>.B, <Pn>.B

SVE_DA_4A

BRKPA   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
BRKPAS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
BRKPB   <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B
BRKPBS  <Pd>.B, <Pg>/Z, <Pn>.B, <Pm>.B

........xx...... ...gggxxiiiddddd

SVE_AM_2A

ASR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
ASRD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
LSL     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
LSR     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
SQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
SQSHLU  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
SRSHR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
UQSHL   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>
URSHR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, #<const>

........xx.xxiii ......nnnnnddddd

SVE_BF_2A

ASR     <Zd>.<T>, <Zn>.<T>, #<const>
LSL     <Zd>.<T>, <Zn>.<T>, #<const>
LSR     <Zd>.<T>, <Zn>.<T>, #<const>

SVE_FT_2A

SLI     <Zd>.<T>, <Zn>.<T>, #<const>
SRI     <Zd>.<T>, <Zn>.<T>, #<const>

SVE_FU_2A

SRSRA   <Zda>.<T>, <Zn>.<T>, #<const>
SSRA    <Zda>.<T>, <Zn>.<T>, #<const>
URSRA   <Zda>.<T>, <Zn>.<T>, #<const>
USRA    <Zda>.<T>, <Zn>.<T>, #<const>

........xx...... ...iiiiiiiiddddd

SVE_EA_1A

FDUP    <Zd>.<T>, #<const>
FMOV    <Zd>.<T>, #<const>

SVE_ED_1A

SMAX    <Zdn>.<T>, <Zdn>.<T>, #<imm>
SMIN    <Zdn>.<T>, <Zdn>.<T>, #<imm>
UMAX    <Zdn>.<T>, <Zdn>.<T>, #<imm>
UMIN    <Zdn>.<T>, <Zdn>.<T>, #<imm>

SVE_EE_1A

MUL     <Zdn>.<T>, <Zdn>.<T>, #<imm>

.........x.mmmmm ....hhnnnnnddddd

SVE_BH_3A

ADR     <Zd>.<T>, [<Zn>.<T>, <Zm>.<T>{, <mod><amount>}]

...........mmmmm ....hhnnnnnddddd

SVE_BH_3B

ADR     <Zd>.D, [<Zn>.D, <Zm>.D, SXTW{<amount>}]

SVE_BH_3B_A

ADR     <Zd>.D, [<Zn>.D, <Zm>.D, UXTW{<amount>}]

................ ...gggmmmmmddddd

SVE_AB_3B

ADDPT   <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D
SUBPT   <Zdn>.D, <Pg>/M, <Zdn>.D, <Zm>.D

SVE_HL_3B

BFADD   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
BFMAX   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
BFMAXNM <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
BFMIN   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
BFMINNM <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
BFMUL   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H
BFSUB   <Zdn>.H, <Pg>/M, <Zdn>.H, <Zm>.H

........xx...... .......NNNN.DDDD

SVE_CJ_2A

REV     <Pd>.<T>, <Pn>.<T>

.........i.iimmm ......nnnnnddddd

SVE_FD_3A

MUL     <Zd>.H, <Zn>.H, <Zm>.H[<imm>]

SVE_FF_3A

MLA     <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
MLS     <Zda>.H, <Zn>.H, <Zm>.H[<imm>]

SVE_FI_3A

SQDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>]
SQRDMULH <Zd>.H, <Zn>.H, <Zm>.H[<imm>]

SVE_FK_3A

SQRDMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
SQRDMLSH <Zda>.H, <Zn>.H, <Zm>.H[<imm>]

SVE_GU_3C

BFMLA   <Zda>.H, <Zn>.H, <Zm>.H[<imm>]
BFMLS   <Zda>.H, <Zn>.H, <Zm>.H[<imm>]

SVE_GX_3C

BFMUL   <Zd>.H, <Zn>.H, <Zm>.H[<imm>]

...........iimmm ......nnnnnddddd

SVE_EG_3A

SDOT    <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
UDOT    <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

SVE_EY_3A

SDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
UDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>]

SVE_EZ_3A

SUDOT   <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
USDOT   <Zda>.S, <Zn>.B, <Zm>.B[<imm>]

SVE_FD_3B

MUL     <Zd>.S, <Zn>.S, <Zm>.S[<imm>]

SVE_FF_3B

MLA     <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
MLS     <Zda>.S, <Zn>.S, <Zm>.S[<imm>]

SVE_FI_3B

SQDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>]
SQRDMULH <Zd>.S, <Zn>.S, <Zm>.S[<imm>]

SVE_FK_3B

SQRDMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
SQRDMLSH <Zda>.S, <Zn>.S, <Zm>.S[<imm>]

SVE_GU_3A

FMLA    <Zda>.S, <Zn>.S, <Zm>.S[<imm>]
FMLS    <Zda>.S, <Zn>.S, <Zm>.S[<imm>]

SVE_GX_3A

FMUL    <Zd>.S, <Zn>.S, <Zm>.S[<imm>]

SVE_GY_3B

BFDOT   <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
FDOT    <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

SVE_GY_3B_D

FDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>]

...........immmm ......nnnnnddddd

SVE_EY_3B

SDOT    <Zda>.D, <Zn>.H, <Zm>.H[<imm>]
UDOT    <Zda>.D, <Zn>.H, <Zm>.H[<imm>]

SVE_FD_3C

MUL     <Zd>.D, <Zn>.D, <Zm>.D[<imm>]

SVE_FF_3C

MLA     <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
MLS     <Zda>.D, <Zn>.D, <Zm>.D[<imm>]

SVE_FI_3C

SQDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>]
SQRDMULH <Zd>.D, <Zn>.D, <Zm>.D[<imm>]

SVE_FK_3C

SQRDMLAH <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
SQRDMLSH <Zda>.D, <Zn>.D, <Zm>.D[<imm>]

SVE_GU_3B

FMLA    <Zda>.D, <Zn>.D, <Zm>.D[<imm>]
FMLS    <Zda>.D, <Zn>.D, <Zm>.D[<imm>]

SVE_GX_3B

FMUL    <Zd>.D, <Zn>.D, <Zm>.D[<imm>]

...........iiiii ...iiinnnnnddddd

SVE_BQ_2A

EXT     <Zd>.B, {<Zn1>.B, <Zn2>.B }, #<imm>

...........iiiii ...iiimmmmmddddd

SVE_BQ_2B

EXT     <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>

........xx..gggg ...iiiiiiiiddddd

SVE_BU_2A

FCPY    <Zd>.<T>, <Pg>/M, #<const>
FMOV    <Zd>.<T>, <Pg>/M, #<const>

........xx..gggg ...........ddddd

SVE_BV_2B

FMOV    <Zd>.<T>, <Pg>/M, #0.0

........xx...... ...........ddddd

SVE_EB_1B

FMOV    <Zd>.<T>, #0.0

........xx..MMMM .......NNNN.DDDD

SVE_CI_3A

TRN1    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
TRN2    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
UZP1    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
UZP2    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
ZIP1    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>
ZIP2    <Pd>.<T>, <Pn>.<T>, <Pm>.<T>

............iiii ......nnnn.ddddd

SVE_GA_2A

SQRSHRN <Zd>.H, {<Zn1>.S-<Zn2>.S }, #<const>
SQRSHRUN <Zd>.H, {<Zn1>.S-<Zn2>.S }, #<const>
UQRSHRN <Zd>.H, {<Zn1>.S-<Zn2>.S }, #<const>

................ ...gggnnnnnddddd

SVE_CT_3A

REVD    <Zd>.Q, <Pg>/M, <Zn>.Q

SVE_GQ_3A

BFCVTNT <Zd>.H, <Pg>/M, <Zn>.S
FCVTLT  <Zd>.D, <Pg>/M, <Zn>.S
FCVTNT  <Zd>.S, <Pg>/M, <Zn>.D
FCVTXNT <Zd>.S, <Pg>/M, <Zn>.D

SVE_HO_3A

BFCVT   <Zd>.H, <Pg>/M, <Zn>.S
FCVT    <Zd>.D, <Pg>/M, <Zn>.S
FCVTX   <Zd>.S, <Pg>/M, <Zn>.D

SVE_HO_3A_B

FCVT    <Zd>.S, <Pg>/M, <Zn>.D

SVE_HP_3B

FCVTZS  <Zd>.S, <Pg>/M, <Zn>.S
FCVTZU  <Zd>.S, <Pg>/M, <Zn>.S

SVE_HP_3B_H

FCVTZS  <Zd>.D, <Pg>/M, <Zn>.S
FCVTZU  <Zd>.D, <Pg>/M, <Zn>.S

SVE_HP_3B_I

FCVTZS  <Zd>.S, <Pg>/M, <Zn>.D
FCVTZU  <Zd>.S, <Pg>/M, <Zn>.D

SVE_HP_3B_J

FCVTZS  <Zd>.D, <Pg>/M, <Zn>.D
FCVTZU  <Zd>.D, <Pg>/M, <Zn>.D

SVE_HS_3A

SCVTF   <Zd>.S, <Pg>/M, <Zn>.S
UCVTF   <Zd>.S, <Pg>/M, <Zn>.S

SVE_HS_3A_H

SCVTF   <Zd>.D, <Pg>/M, <Zn>.S
UCVTF   <Zd>.D, <Pg>/M, <Zn>.S

SVE_HS_3A_I

SCVTF   <Zd>.S, <Pg>/M, <Zn>.D
UCVTF   <Zd>.S, <Pg>/M, <Zn>.D

SVE_HS_3A_J

SCVTF   <Zd>.D, <Pg>/M, <Zn>.D
UCVTF   <Zd>.D, <Pg>/M, <Zn>.D

........xx...... ...gggnnnnn.DDDD

SVE_HI_3A

FCMEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
FCMGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
FCMGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
FCMLE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
FCMLT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0
FCMNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #0.0

........xx.mmmmm ...gggnnnnn.DDDD

SVE_CX_4A

CMPEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
CMPGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
CMPGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
CMPHI   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
CMPHS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
CMPLE   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
CMPLO   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
CMPLS   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
CMPLT   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
CMPNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

SVE_CX_4A_A

CMPEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPHI   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPHS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPLE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPLO   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPLS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPLT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D
CMPNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.D

SVE_GE_4A

MATCH   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
NMATCH  <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

SVE_HT_4A

FACGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
FACGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
FACLE   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
FACLT   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
FCMEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
FCMGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
FCMGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
FCMLE   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
FCMLT   <Pd>.<T>, <Pg>/Z, <Zm>.<T>, <Zn>.<T>
FCMNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>
FCMUO   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

........xx.mmmmm ...gggnnnnnddddd

SVE_AR_4A

MLA     <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
MLS     <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>

SVE_GI_4A

HISTCNT <Zd>.<T>, <Pg>/Z, <Zn>.<T>, <Zm>.<T>

SVE_HU_4A

FMLA    <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
FMLS    <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
FNMLA   <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>
FNMLS   <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>

........xx...... ...ggg....iddddd

SVE_HM_2A

FADD    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
FMAX    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
FMAXNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
FMIN    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
FMINNM  <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
FMUL    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
FSUB    <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>
FSUBR   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <const>

........i..mmmmm ......nnnnnddddd

SVE_GH_3A

LUTI4   <Zd>.B, {<Zn>.B }, <Zm>[<index>]

........ii.mmmmm ......nnnnnddddd

SVE_GG_3A

LUTI2   <Zd>.B, {<Zn>.B }, <Zm>[<index>]

SVE_GH_3B

LUTI4   <Zd>.H, {<Zn1>.H, <Zn2>.H }, <Zm>[<index>]

SVE_GH_3B_B

LUTI4   <Zd>.H, {<Zn>.H }, <Zm>[<index>]

........ii.mmmmm ...i..nnnnnddddd

SVE_GG_3B

LUTI2   <Zd>.H, {<Zn>.H }, <Zm>[<index>]

...........mmmmm ......kkkkkddddd

SVE_AV_3A

BCAX    <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
BSL     <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
BSL1N   <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
BSL2N   <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
EOR3    <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D
NBSL    <Zdn>.D, <Zdn>.D, <Zm>.D, <Zk>.D

................ ......nnnn.ddddd

SVE_FZ_2A

SQCVTN  <Zd>.H, {<Zn1>.S-<Zn2>.S }
SQCVTUN <Zd>.H, {<Zn1>.S-<Zn2>.S }
UQCVTN  <Zd>.H, {<Zn1>.S-<Zn2>.S }

SVE_HG_2A

BFCVTN  <Zd>.B, {<Zn1>.H-<Zn2>.H }
FCVTN   <Zd>.B, {<Zn1>.H-<Zn2>.H }
FCVTNB  <Zd>.B, {<Zn1>.S-<Zn2>.S }
FCVTNT  <Zd>.B, {<Zn1>.S-<Zn2>.S }

...........iimmm ....i.nnnnnddddd

SVE_FE_3A

SMULLB  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
SMULLT  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
UMULLB  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
UMULLT  <Zd>.S, <Zn>.H, <Zm>.H[<imm>]

SVE_FG_3A

SMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
SMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
SMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
SMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
UMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
UMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
UMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
UMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

SVE_FH_3A

SQDMULLB <Zd>.S, <Zn>.H, <Zm>.H[<imm>]
SQDMULLT <Zd>.S, <Zn>.H, <Zm>.H[<imm>]

SVE_FJ_3A

SQDMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
SQDMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
SQDMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
SQDMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

SVE_GY_3A

FDOT    <Zda>.H, <Zn>.B, <Zm>.B[<imm>]

SVE_GZ_3A

BFMLALB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
BFMLALT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
BFMLSLB <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
BFMLSLT <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
FMLALB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
FMLALT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
FMLSLB  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]
FMLSLT  <Zda>.S, <Zn>.H, <Zm>.H[<imm>]

........xx.mmmmm .rrgggnnnnnddddd

SVE_GT_4A

FCMLA   <Zda>.<T>, <Pg>/M, <Zn>.<T>, <Zm>.<T>, <const>

...........immmm ....rrnnnnnddddd

SVE_FA_3B

CDOT    <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const>

SVE_FB_3B

CMLA    <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>

SVE_FC_3B

SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>

SVE_GV_3A

FCMLA   <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>

........xx.....r ...gggmmmmmddddd

SVE_GP_3A

FCADD   <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>, <const>

...........iimmm ....iinnnnnddddd

SVE_GM_3A

FMLALB  <Zda>.H, <Zn>.B, <Zm>.B[<imm>]
FMLALT  <Zda>.H, <Zn>.B, <Zm>.B[<imm>]

SVE_HC_3A

FMLALLBB <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
FMLALLBT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
FMLALLTB <Zda>.S, <Zn>.B, <Zm>.B[<imm>]
FMLALLTT <Zda>.S, <Zn>.B, <Zm>.B[<imm>]

................ ......mmmmmddddd

SVE_GK_2A

AESD    <Zdn>.B, <Zdn>.B, <Zm>.B
AESE    <Zdn>.B, <Zdn>.B, <Zm>.B
SM4E    <Zdn>.S, <Zdn>.S, <Zm>.S

................ ...........ddddd

SVE_GL_1A

AESIMC  <Zdn>.B, <Zdn>.B
AESMC   <Zdn>.B, <Zdn>.B

........xx.xxiii ......mmmmmddddd

SVE_AW_2A

XAR     <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<const>

........xx.....M ...gggnnnnnddddd

SVE_AH_3A

MOVPRFX <Zd>.<T>, <Pg>/<ZM>, <Zn>.<T>

................ ......nnnnnddddd

SVE_BI_2A

MOVPRFX <Zd>, <Zn>

SVE_HH_2A

BF1CVT  <Zd>.H, <Zn>.B
BF1CVTLT <Zd>.H, <Zn>.B
BF2CVT  <Zd>.H, <Zn>.B
BF2CVTLT <Zd>.H, <Zn>.B
F1CVT   <Zd>.H, <Zn>.B
F1CVTLT <Zd>.H, <Zn>.B
F2CVT   <Zd>.H, <Zn>.B
F2CVTLT <Zd>.H, <Zn>.B

........xx.mmmmm ...gggaaaaaddddd

SVE_AS_4A

MAD     <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
MSB     <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>

........xx.iiiii ......iiiiiddddd

SVE_AX_1A

INDEX   <Zd>.<T>, #<imm1>, #<imm2>

........xx.mmmmm ......iiiiiddddd

SVE_AY_2A

INDEX   <Zd>.<T>, #<imm>, <R><m>

........xx.iiiii ......nnnnnddddd

SVE_AZ_2A

INDEX   <Zd>.<T>, <R><n>, #<imm>

...........nnnnn .....iiiiiiddddd

SVE_BB_2A

ADDPL   <Xd|SP>, <Xn|SP>, #<imm>
ADDVL   <Xd|SP>, <Xn|SP>, #<imm>

................ .....iiiiiiddddd

SVE_BC_1A

RDVL    <Xd>, #<imm>

............iiii ......pppppddddd

SVE_BL_1A

CNTB    <Xd>{, <pattern>{, MUL #<imm>}}
CNTD    <Xd>{, <pattern>{, MUL #<imm>}}
CNTH    <Xd>{, <pattern>{, MUL #<imm>}}
CNTW    <Xd>{, <pattern>{, MUL #<imm>}}

SVE_BM_1A

DECB    <Xdn>{, <pattern>{, MUL #<imm>}}
DECD    <Xdn>{, <pattern>{, MUL #<imm>}}
DECH    <Xdn>{, <pattern>{, MUL #<imm>}}
DECW    <Xdn>{, <pattern>{, MUL #<imm>}}
INCB    <Xdn>{, <pattern>{, MUL #<imm>}}
INCD    <Xdn>{, <pattern>{, MUL #<imm>}}
INCH    <Xdn>{, <pattern>{, MUL #<imm>}}
INCW    <Xdn>{, <pattern>{, MUL #<imm>}}

SVE_BN_1A

DECD    <Zdn>.D{, <pattern>{, MUL #<imm>}}
DECH    <Zdn>.H{, <pattern>{, MUL #<imm>}}
DECW    <Zdn>.S{, <pattern>{, MUL #<imm>}}
INCD    <Zdn>.D{, <pattern>{, MUL #<imm>}}
INCH    <Zdn>.H{, <pattern>{, MUL #<imm>}}
INCW    <Zdn>.S{, <pattern>{, MUL #<imm>}}

SVE_BP_1A

SQDECD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
SQDECH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
SQDECW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
SQINCD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
SQINCH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
SQINCW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
UQDECD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
UQDECH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
UQDECW  <Zdn>.S{, <pattern>{, MUL #<imm>}}
UQINCD  <Zdn>.D{, <pattern>{, MUL #<imm>}}
UQINCH  <Zdn>.H{, <pattern>{, MUL #<imm>}}
UQINCW  <Zdn>.S{, <pattern>{, MUL #<imm>}}

...........Xiiii ......pppppddddd

SVE_BO_1A

SQDECB  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
SQDECD  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
SQDECH  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
SQDECW  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
SQINCB  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
SQINCD  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
SQINCH  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
SQINCW  <Xdn>, <Wdn>{, <pattern>{, MUL #<imm>}}
UQDECB  <Wdn>{, <pattern>{, MUL #<imm>}}
UQDECD  <Wdn>{, <pattern>{, MUL #<imm>}}
UQDECH  <Wdn>{, <pattern>{, MUL #<imm>}}
UQDECW  <Wdn>{, <pattern>{, MUL #<imm>}}
UQINCB  <Wdn>{, <pattern>{, MUL #<imm>}}
UQINCD  <Wdn>{, <pattern>{, MUL #<imm>}}
UQINCH  <Wdn>{, <pattern>{, MUL #<imm>}}
UQINCW  <Wdn>{, <pattern>{, MUL #<imm>}}

...........ixxxx ......nnnnnddddd

SVE_BX_2A

DUPQ    <Zd>.<T>, <Zn>.<T>[<imm>]

............iiii ......mmmmmddddd

SVE_BY_2A

EXTQ    <Zdn>.B, <Zdn>.B, <Zm>.B, #<imm>

........xx...... ......mmmmmddddd

SVE_CC_2A

INSR    <Zdn>.<T>, <V><m>

SVE_CD_2A

INSR    <Zdn>.<T>, <R><m>

................ ......nnnnn.DDDD

SVE_CE_2A

PMOV    <Pd>.B, <Zn>

.........i...ii. ......nnnnn.DDDD

SVE_CE_2B

PMOV    <Pd>.D, <Zn>[<imm>]

..............i. ......nnnnn.DDDD

SVE_CE_2C

PMOV    <Pd>.H, <Zn>[<imm>]

.............ii. ......nnnnn.DDDD

SVE_CE_2D

PMOV    <Pd>.S, <Zn>[<imm>]

................ .......NNNNddddd

SVE_CF_2A

PMOV    <Zd>, <Pn>.B

.........i...ii. .......NNNNddddd

SVE_CF_2B

PMOV    <Zd>[<imm>], <Pn>.D

..............i. .......NNNNddddd

SVE_CF_2C

PMOV    <Zd>[<imm>], <Pn>.H

.............ii. .......NNNNddddd

SVE_CF_2D

PMOV    <Zd>[<imm>], <Pn>.S

................ .......NNNN.DDDD

SVE_CK_2A

PUNPKHI <Pd>.H, <Pn>.B
PUNPKLO <Pd>.H, <Pn>.B

........xx...... ...VVVnnnnnddddd

SVE_CV_3A

SPLICE  <Zd>.<T>, <Pv>, {<Zn1>.<T>, <Zn2>.<T>}

........xx...... ...VVVmmmmmddddd

SVE_CV_3B

SPLICE  <Zdn>.<T>, <Pv>, <Zdn>.<T>, <Zm>.<T>

........xx.iiiii ...gggnnnnn.DDDD

SVE_CY_3A

CMPEQ   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPGE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPGT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPLE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPLT   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPNE   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>

........xx.iiiii ii.gggnnnnn.DDDD

SVE_CY_3B

CMPHI   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPHS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPLO   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>
CMPLS   <Pd>.<T>, <Pg>/Z, <Zn>.<T>, #<imm>

................ ..gggg.NNNNMDDDD

SVE_DB_3A

BRKA    <Pd>.B, <Pg>/<ZM>, <Pn>.B
BRKB    <Pd>.B, <Pg>/<ZM>, <Pn>.B

................ ..gggg.NNNN.DDDD

SVE_DB_3B

BRKAS   <Pd>.B, <Pg>/Z, <Pn>.B
BRKBS   <Pd>.B, <Pg>/Z, <Pn>.B

................ ..gggg.NNNN.MMMM

SVE_DC_3A

BRKN    <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B
BRKNS   <Pdm>.B, <Pg>/Z, <Pn>.B, <Pdm>.B

................ .......gggg.DDDD

SVE_DD_2A

PFIRST  <Pdn>.B, <Pg>, <Pdn>.B

SVE_DG_2A

RDFFR   <Pd>.B, <Pg>/Z
RDFFRS  <Pd>.B, <Pg>/Z

........xx...... ......ppppp.DDDD

SVE_DE_1A

PTRUE   <Pd>.<T>{, <pattern>}
PTRUES  <Pd>.<T>{, <pattern>}

........xx...... .............DDD

SVE_DZ_1A

PTRUE   <PNd>.<T>

........xx...... .......VVVV.DDDD

SVE_DF_2A

PNEXT   <Pdn>.<T>, <Pv>, <Pdn>.<T>

................ ............DDDD

SVE_DH_1A

RDFFR   <Pd>.B

SVE_DJ_1A

PFALSE  <Pd>.B

................ ..gggg.NNNN.....

SVE_DI_2A

PTEST   <Pg>, <Pn>.B

........xx...... ..gggg.NNNNddddd

SVE_DK_3A

CNTP    <Xd>, <Pg>, <Pn>.<T>

........xx...... .....l.NNNNddddd

SVE_DL_2A

CNTP    <Xd>, <PNn>.<T>, <vl>

........xx...... .......MMMMddddd

SVE_DM_2A

DECP    <Xdn>, <Pm>.<T>
INCP    <Xdn>, <Pm>.<T>

SVE_DN_2A

DECP    <Zdn>.<T>, <Pm>.<T>
INCP    <Zdn>.<T>, <Pm>.<T>

SVE_DP_2A

SQDECP  <Zdn>.<T>, <Pm>.<T>
SQINCP  <Zdn>.<T>, <Pm>.<T>
UQDECP  <Zdn>.<T>, <Pm>.<T>
UQINCP  <Zdn>.<T>, <Pm>.<T>

........xx...... .....X.MMMMddddd

SVE_DO_2A

SQDECP  <Xdn>, <Pm>.<T>, <Wdn>
SQINCP  <Xdn>, <Pm>.<T>, <Wdn>
UQDECP  <Wdn>, <Pm>.<T>
UQINCP  <Wdn>, <Pm>.<T>

................ ................

SVE_DQ_0A

SETFFR  

................ .......NNNN.....

SVE_DR_1A

WRFFR   <Pn>.B

.........x.mmmmm ......nnnnn.....

SVE_DS_2A

CTERMEQ <R><n>, <R><m>
CTERMNE <R><n>, <R><m>

........xx.mmmmm ...X..nnnnn.DDDD

SVE_DT_3A

WHILEGE <Pd>.<T>, <R><n>, <R><m>
WHILEGT <Pd>.<T>, <R><n>, <R><m>
WHILEHI <Pd>.<T>, <R><n>, <R><m>
WHILEHS <Pd>.<T>, <R><n>, <R><m>
WHILELE <Pd>.<T>, <R><n>, <R><m>
WHILELO <Pd>.<T>, <R><n>, <R><m>
WHILELS <Pd>.<T>, <R><n>, <R><m>
WHILELT <Pd>.<T>, <R><n>, <R><m>

........xx.mmmmm ......nnnnn.DDD.

SVE_DX_3A

WHILEGE {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
WHILEGT {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
WHILEHI {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
WHILEHS {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
WHILELE {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
WHILELO {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
WHILELS {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>
WHILELT {<Pd1>.<T>, <Pd2>.<T>}, <Xn>, <Xm>

........xx.mmmmm ..l...nnnnn..DDD

SVE_DY_3A

WHILEGE <PNd>.<T>, <Xn>, <Xm>, <vl>
WHILEGT <PNd>.<T>, <Xn>, <Xm>, <vl>
WHILEHI <PNd>.<T>, <Xn>, <Xm>, <vl>
WHILEHS <PNd>.<T>, <Xn>, <Xm>, <vl>
WHILELE <PNd>.<T>, <Xn>, <Xm>, <vl>
WHILELO <PNd>.<T>, <Xn>, <Xm>, <vl>
WHILELS <PNd>.<T>, <Xn>, <Xm>, <vl>
WHILELT <PNd>.<T>, <Xn>, <Xm>, <vl>

........xx.mmmmm ......nnnnn.DDDD

SVE_DU_3A

WHILERW <Pd>.<T>, <Xn>, <Xm>
WHILEWR <Pd>.<T>, <Xn>, <Xm>

........ix.xxxvv ..NNNN.MMMM.DDDD

SVE_DV_4A

PSEL    <Pd>, <Pn>, <Pm>.<T>[<Wv>, <imm>]

........xx...... ......iiNNN.DDDD

SVE_DW_2A

PEXT    <Pd>.<T>, <PNn>[<imm>]

........xx...... .......iNNN.DDDD

SVE_DW_2B

PEXT    {<Pd1>.<T>, <Pd2>.<T>}, <PNn>[<imm>]

........xx.mmmmm ....rrnnnnnddddd

SVE_EJ_3A

CDOT    <Zda>.<T>, <Zn>.<Tb>, <Zm>.<Tb>, <const>

SVE_EK_3A

CMLA    <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>

...........iimmm ....rrnnnnnddddd

SVE_FA_3A

CDOT    <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const>

SVE_FB_3A

CMLA    <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>

SVE_FC_3A

SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>

...........immmm ....i.nnnnnddddd

SVE_FE_3B

SMULLB  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
SMULLT  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
UMULLB  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
UMULLT  <Zd>.D, <Zn>.S, <Zm>.S[<imm>]

SVE_FG_3B

SMLALB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
SMLALT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
SMLSLB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
SMLSLT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
UMLALB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
UMLALT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
UMLSLB  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
UMLSLT  <Zda>.D, <Zn>.S, <Zm>.S[<imm>]

SVE_FH_3B

SQDMULLB <Zd>.D, <Zn>.S, <Zm>.S[<imm>]
SQDMULLT <Zd>.D, <Zn>.S, <Zm>.S[<imm>]

SVE_FJ_3B

SQDMLALB <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
SQDMLALT <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
SQDMLSLB <Zda>.D, <Zn>.S, <Zm>.S[<imm>]
SQDMLSLT <Zda>.D, <Zn>.S, <Zm>.S[<imm>]

...........mmmmm ......aaaaaddddd

SVE_EW_3B

MADPT   <Zdn>.D, <Zm>.D, <Za>.D

.........x.xxiii ......nnnnnddddd

SVE_FR_2A

SSHLLB  <Zd>.<T>, <Zn>.<Tb>, #<const>
SSHLLT  <Zd>.<T>, <Zn>.<Tb>, #<const>
USHLLB  <Zd>.<T>, <Zn>.<Tb>, #<const>
USHLLT  <Zd>.<T>, <Zn>.<Tb>, #<const>

SVE_GB_2A

RSHRNB  <Zd>.<T>, <Zn>.<Tb>, #<const>
RSHRNT  <Zd>.<T>, <Zn>.<Tb>, #<const>
SHRNB   <Zd>.<T>, <Zn>.<Tb>, #<const>
SHRNT   <Zd>.<T>, <Zn>.<Tb>, #<const>
SQRSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
SQRSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>
SQRSHRUNB <Zd>.<T>, <Zn>.<Tb>, #<const>
SQRSHRUNT <Zd>.<T>, <Zn>.<Tb>, #<const>
SQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
SQSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>
SQSHRUNB <Zd>.<T>, <Zn>.<Tb>, #<const>
SQSHRUNT <Zd>.<T>, <Zn>.<Tb>, #<const>
UQRSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
UQRSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>
UQSHRNB <Zd>.<T>, <Zn>.<Tb>, #<const>
UQSHRNT <Zd>.<T>, <Zn>.<Tb>, #<const>

........xx...... .....rmmmmmddddd

SVE_FV_2A

CADD    <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
SQCADD  <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>

.........x.mmmmm ......nnnnnddddd

SVE_FY_3A

ADCLB   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
ADCLT   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
SBCLB   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>
SBCLT   <Zda>.<T>, <Zn>.<T>, <Zm>.<T>

.........x.xx... ......nnnnnddddd

SVE_GD_2A

SQXTNB  <Zd>.<T>, <Zn>.<Tb>
SQXTNT  <Zd>.<T>, <Zn>.<Tb>
SQXTUNB <Zd>.<T>, <Zn>.<Tb>
SQXTUNT <Zd>.<T>, <Zn>.<Tb>
UQXTNB  <Zd>.<T>, <Zn>.<Tb>
UQXTNT  <Zd>.<T>, <Zn>.<Tb>

...........mmmmm ...gggnnnnnddddd

SVE_HU_4B

BFMLA   <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H
BFMLS   <Zda>.H, <Pg>/M, <Zn>.H, <Zm>.H

........xx...iii ......mmmmmddddd

SVE_HN_2A

FTMAD   <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, #<imm>

.............xx. ...gggnnnnnddddd

SVE_HP_3A

FLOGB   <Zd>.<T>, <Pg>/M, <Zn>.<T>

........xx.aaaaa ...gggmmmmmddddd

SVE_HV_4A

FMAD    <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
FMSB    <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
FNMAD   <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>
FNMSB   <Zdn>.<T>, <Pg>/M, <Zm>.<T>, <Za>.<T>

.........h.mmmmm ...gggnnnnnttttt

SVE_HW_4A

LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LD1H    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LD1SH   {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
LD1W    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2]
LDFF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LDFF1H  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
LDFF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LDFF1SH {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #1]
LDFF1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod> #2]

SVE_HW_4A_A

LD1B    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
LD1SB   {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
LDFF1B  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
LDFF1SB {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #1]
LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]

SVE_HW_4A_B

LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]

SVE_HW_4A_C

LD1H    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LD1SH   {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LD1W    {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LDFF1H  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LDFF1SH {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]
LDFF1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Zm>.S, <mod>]

SVE_IU_4A

LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3]
LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]
LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #3]
LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod> #2]

SVE_IU_4A_A

LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]
LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]

SVE_IU_4A_C

LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, <mod>]

...........mmmmm ...gggnnnnnttttt

SVE_HW_4B

LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
LDFF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
LDFF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #1]
LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]

SVE_HW_4B_D

LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]

SVE_IF_4A

LDNT1B  {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
LDNT1H  {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
LDNT1SB {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
LDNT1SH {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]
LDNT1W  {<Zt>.S }, <Pg>/Z, [<Zn>.S{, <Xm>}]

SVE_IF_4A_A

LDNT1B  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
LDNT1H  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
LDNT1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
LDNT1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
LDNT1W  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]

SVE_IG_4A

LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #3}]
LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]

SVE_IG_4A_D

LDFF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]

SVE_IG_4A_E

LDFF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>}]

SVE_IG_4A_F

LDFF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]
LDFF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #2}]

SVE_IG_4A_G

LDFF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, <Xm>, LSL #1}]

SVE_II_4A

LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]

SVE_II_4A_B

LD1D    {<Zt>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]

SVE_II_4A_H

LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

SVE_IK_4A

LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

SVE_IK_4A_F

LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]

SVE_IK_4A_G

LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]

SVE_IK_4A_H

LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>]

SVE_IK_4A_I

LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]

SVE_IN_4A

LDNT1B  {<Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
LDNT1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LDNT1H  {<Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LDNT1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

SVE_IP_4A

LD1ROB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
LD1ROD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD1ROH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD1ROW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD1RQB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
LD1RQD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD1RQH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD1RQW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

SVE_IR_4A

LD2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
LD3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]
LD4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #4]

SVE_IT_4A

LD2B    {<Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
LD2D    {<Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD2H    {<Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD2W    {<Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
LD3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]
LD4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>, <Xm>]
LD4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #3]
LD4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #1]
LD4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>, <Xm>, LSL #2]

SVE_IU_4B

LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]
LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #3]
LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D, LSL #2]

SVE_IU_4B_B

LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LDFF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]
LDFF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]

SVE_IU_4B_D

LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>, <Zm>.D]

SVE_IW_4A

LD1Q    {<Zt>.Q }, <Pg>/Z, [<Zn>.D{, <Xm>}]

SVE_IX_4A

LDNT1D  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]
LDNT1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, <Xm>}]

SVE_IY_4A

ST1Q    {<Zt>.Q }, <Pg>, [<Zn>.D{, <Xm>}]

SVE_IZ_4A

STNT1B  {<Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
STNT1H  {<Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]
STNT1W  {<Zt>.S }, <Pg>, [<Zn>.S{, <Xm>}]

SVE_IZ_4A_A

STNT1B  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
STNT1H  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]
STNT1W  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]

SVE_JA_4A

STNT1D  {<Zt>.D }, <Pg>, [<Zn>.D{, <Xm>}]

SVE_JB_4A

STNT1B  {<Zt>.B }, <Pg>, [<Xn|SP>, <Xm>]
STNT1D  {<Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
STNT1H  {<Zt>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
STNT1W  {<Zt>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

SVE_JC_4A

ST2B    {<Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>, <Xm>]
ST2D    {<Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST2H    {<Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
ST2W    {<Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
ST3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>, <Xm>]
ST3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
ST3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]
ST4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>, <Xm>]
ST4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
ST4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

SVE_JD_4C

ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
ST1W    {<Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

SVE_JD_4C_A

ST1D    {<Zt>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #3]

SVE_JF_4A

ST2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
ST3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]
ST4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>, <Xm>, LSL #4]

SVE_JJ_4B

ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]

SVE_JJ_4B_C

ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]

SVE_JJ_4B_E

ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]
ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]

SVE_JK_4B

ST1B    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D]

...........iiiii ...gggnnnnnttttt

SVE_HX_3A_B

LD1B    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LD1SB   {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LDFF1B  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LDFF1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]

SVE_HX_3A_E

LD1H    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LD1SH   {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LD1W    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LDFF1H  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LDFF1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LDFF1W  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]

SVE_IV_3A

LD1D    {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LD1SW   {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LDFF1D  {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
LDFF1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]

SVE_JI_3A_A

ST1B    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
ST1H    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
ST1W    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]

SVE_JL_3A

ST1D    {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]

............iiii ...gggnnnnnttttt

SVE_IH_3A

LD1D    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IH_3A_A

LD1D    {<Zt>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IH_3A_F

LD1W    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IJ_3A

LD1SW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IJ_3A_D

LD1SB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IJ_3A_E

LD1B    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IJ_3A_F

LD1SH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IJ_3A_G

LD1H    {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IL_3A

LDNF1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LDNF1SW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IL_3A_A

LDNF1SH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LDNF1W  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IL_3A_B

LDNF1H  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LDNF1SB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IL_3A_C

LDNF1B  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IM_3A

LDNT1B  {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LDNT1D  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LDNT1H  {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LDNT1W  {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IO_3A

LD1ROB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1ROD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1ROH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1ROW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1RQB  {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1RQD  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1RQH  {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1RQW  {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

SVE_IQ_3A

LD2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_IS_3A

LD2B    {<Zt1>.B, <Zt2>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD2D    {<Zt1>.D, <Zt2>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD2H    {<Zt1>.H, <Zt2>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD2W    {<Zt1>.S, <Zt2>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]
LD4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_JE_3A

ST2Q    {<Zt1>.Q, <Zt2>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST3Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST4Q    {<Zt1>.Q, <Zt2>.Q, <Zt3>.Q, <Zt4>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_JM_3A

STNT1B  {<Zt>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
STNT1D  {<Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
STNT1H  {<Zt>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
STNT1W  {<Zt>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_JN_3C

ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST1W    {<Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_JN_3C_D

ST1D    {<Zt>.Q }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

SVE_JO_3A

ST2B    {<Zt1>.B, <Zt2>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST2D    {<Zt1>.D, <Zt2>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST2H    {<Zt1>.H, <Zt2>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST2W    {<Zt1>.S, <Zt2>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST3B    {<Zt1>.B, <Zt2>.B, <Zt3>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST3D    {<Zt1>.D, <Zt2>.D, <Zt3>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST3H    {<Zt1>.H, <Zt2>.H, <Zt3>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST3W    {<Zt1>.S, <Zt2>.S, <Zt3>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST4B    {<Zt1>.B, <Zt2>.B, <Zt3>.B, <Zt4>.B }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST4D    {<Zt1>.D, <Zt2>.D, <Zt3>.D, <Zt4>.D }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST4H    {<Zt1>.H, <Zt2>.H, <Zt3>.H, <Zt4>.H }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST4W    {<Zt1>.S, <Zt2>.S, <Zt3>.S, <Zt4>.S }, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

.........h.mmmmm ...gggnnnnn.oooo

SVE_HY_3A

PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #3]
PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]

SVE_HY_3A_A

PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]

...........mmmmm ...gggnnnnn.oooo

SVE_HY_3B

PRFB    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D]
PRFD    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #3]
PRFH    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #1]
PRFW    <prfop>, <Pg>, [<Xn|SP>, <Zm>.D, LSL #2]

SVE_IB_3A

PRFB    <prfop>, <Pg>, [<Xn|SP>, <Xm>]
PRFD    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #3]
PRFH    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #1]
PRFW    <prfop>, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

..........iiiiii ...gggnnnnn.oooo

SVE_IA_2A

PRFB    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
PRFD    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
PRFH    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
PRFW    <prfop>, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

...........iiiii ...gggnnnnn.oooo

SVE_HZ_2A_B

PRFB    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
PRFD    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
PRFH    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]
PRFW    <prfop>, <Pg>, [<Zn>.D{, #<imm>}]

..........iiiiii ...gggnnnnnttttt

SVE_IC_3A

LD1RD   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1RSW  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

SVE_IC_3A_A

LD1RSH  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1RW   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

SVE_IC_3A_B

LD1RH   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
LD1RSB  {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

SVE_IC_3A_C

LD1RB   {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

.........xxmmmmm ...gggnnnnnttttt

SVE_JD_4A

ST1B    {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>]
ST1H    {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #1]

...........mmmmm .h.gggnnnnnttttt

SVE_JJ_4A

ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #3]
ST1H    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #1]
ST1W    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod> #2]

SVE_JJ_4A_B

ST1D    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #1]
ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod> #2]

SVE_JJ_4A_C

ST1H    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]
ST1W    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]

SVE_JJ_4A_D

ST1H    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]
ST1W    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]

SVE_JK_4A

ST1B    {<Zt>.D }, <Pg>, [<Xn|SP>, <Zm>.D, <mod>]

SVE_JK_4A_B

ST1B    {<Zt>.S }, <Pg>, [<Xn|SP>, <Zm>.S, <mod>]

.........xx.iiii ...gggnnnnnttttt

SVE_JN_3A

ST1B    {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]
ST1H    {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

..........xmmmmm ...gggnnnnnttttt

SVE_JD_4B

ST1W    {<Zt>.<T>}, <Pg>, [<Xn|SP>, <Xm>, LSL #2]

..........x.iiii ...gggnnnnnttttt

SVE_JN_3B

ST1W    {<Zt>.<T>}, <Pg>, [<Xn|SP>{, #<imm>, MUL VL}]

Contributes to #93095

Assignments

Alan Hayward (@a74nh)

Unique entries= 61, Total formats= 181

• SVE_AA_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_AB_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_AC_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_AD_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_AE_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_AN_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_AO_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_CM_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_CN_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_CO_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_EP_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_ER_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_ET_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_EU_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_GR_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_HJ_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_HL_3A Add Arm64 encodings for IF_SVE_AA_3A to IF_SVE_HL_3A #95127
• SVE_AB_3B JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_HL_3B JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_AF_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_AG_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_AI_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_AJ_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_AK_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_AL_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_AP_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_AQ_3A Add Arm64 encodings for IF_SVE_AF_3A to IF_SVE_AQ_3A #95337
• SVE_CL_3A Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514
• SVE_CP_3A Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514
• SVE_CQ_3A Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514
• SVE_CR_3A Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514
• SVE_CS_3A Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514
• SVE_CU_3A Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514
• SVE_EQ_3A Add Arm64 encodings for IF_SVE_EQ_3A to IF_SVE_HR_3A #95679
• SVE_ES_3A Add Arm64 encodings for IF_SVE_EQ_3A to IF_SVE_HR_3A #95679
• SVE_GS_3A Add Arm64 encodings for IF_SVE_EQ_3A to IF_SVE_HR_3A #95679
• SVE_HE_3A Add Arm64 encodings for IF_SVE_EQ_3A to IF_SVE_HR_3A #95679
• SVE_HQ_3A Add Arm64 encodings for IF_SVE_EQ_3A to IF_SVE_HR_3A #95679
• SVE_HR_3A Add Arm64 encodings for IF_SVE_EQ_3A to IF_SVE_HR_3A #95679
• SVE_AH_3A Add Arm64 encodings for IF_SVE_AH_3A #95864
• SVE_AM_2A Add Arm64 encodings for IF_SVE_AM_2A #95957
• SVE_AR_4A Add Arm64 encodings for IF_SVE_AR_4A, IF_SVE_AS_4A #96165
• SVE_GI_4A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_HU_4A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_AS_4A Add Arm64 encodings for IF_SVE_AR_4A, IF_SVE_AS_4A #96165
• SVE_AT_3A Add Arm64 encodings for IF_SVE_AT_3A to IF_SVE_BK_3A #97082
• SVE_BA_3A Add Arm64 encodings for IF_SVE_AT_3A to IF_SVE_BK_3A #97082
• SVE_BD_3A Add Arm64 encodings for IF_SVE_AT_3A to IF_SVE_BK_3A #97082
• SVE_BE_3A Add Arm64 encodings for IF_SVE_AT_3A to IF_SVE_BK_3A #97082
• SVE_BG_3A Add Arm64 encodings for IF_SVE_AT_3A to IF_SVE_BK_3A #97082
• SVE_BK_3A Add Arm64 encodings for IF_SVE_AT_3A to IF_SVE_BK_3A #97082
• SVE_BR_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_BZ_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_BZ_3A_A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_CA_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EH_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EL_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EM_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EN_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EO_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EV_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EX_3A JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_FL_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FM_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FN_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FP_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FQ_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FS_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FW_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FX_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_GC_3A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_GF_3A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_GW_3A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_HK_3A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_AT_3B JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_AU_3A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_BD_3B JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_BR_3B JIT ARM64_SVE: Add IF_SVE_BR_3A to IF_SVE_EX_3A #98722
• SVE_EF_3A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_EI_3A JIT ARM64-SVE: Add AB_3B to EI_3A #99017
• SVE_EW_3A - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_FN_3B JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_FO_3A JIT ARM64-SVE: Add encodings FL_3A to FX_3A #98832
• SVE_GJ_3A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_GN_3A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_GO_3A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_GW_3B JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_HA_3A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_HA_3A_E JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_HA_3A_F JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_HB_3A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_HD_3A_A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_HK_3B JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_AV_3A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_AW_2A JIT ARM64-SVE: Add AW_2A to AZ_2A, BM_1A, BN_1A #99211
• SVE_AX_1A JIT ARM64-SVE: Add AW_2A to AZ_2A, BM_1A, BN_1A #99211
• SVE_AY_2A JIT ARM64-SVE: Add AW_2A to AZ_2A, BM_1A, BN_1A #99211
• SVE_AZ_2A JIT ARM64-SVE: Add AW_2A to AZ_2A, BM_1A, BN_1A #99211
• SVE_BB_2A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_BC_1A JIT ARM64-SVE: Add GJ_3A to AV_3A, BB_2A and BC_1A #99062
• SVE_BF_2A - JIT: ARM64 SVE format encodings, SVE_BF_2A to SVE_FU_2A #98968
• SVE_FT_2A - JIT: ARM64 SVE format encodings, SVE_BF_2A to SVE_FU_2A #98968
• SVE_FU_2A - JIT: ARM64 SVE format encodings, SVE_BF_2A to SVE_FU_2A #98968
• SVE_BH_3A - Add ARM64 encodings for group IF_SVE_BH_3A,3B,3B_A #98764
• SVE_BH_3B - Add ARM64 encodings for group IF_SVE_BH_3A,3B,3B_A #98764
• SVE_BH_3B_A - Add ARM64 encodings for group IF_SVE_BH_3A,3B,3B_A #98764
• SVE_BI_2A - JIT: ARM64 SVE format encodings, SVE_BI_2A to SVE_HF_2A #98784
• SVE_HH_2A - JIT: ARM64 SVE format encodings, SVE_BI_2A to SVE_HF_2A #98784
• SVE_BJ_2A - JIT: ARM64 SVE format encodings, SVE_BI_2A to SVE_HF_2A #98784
• SVE_CB_2A - JIT: ARM64 SVE format encodings, SVE_BI_2A to SVE_HF_2A #98784
• SVE_CG_2A - JIT: ARM64 SVE format encodings, SVE_BI_2A to SVE_HF_2A #98784
• SVE_CH_2A - JIT: ARM64 SVE format encodings, SVE_BI_2A to SVE_HF_2A #98784
• SVE_HF_2A - JIT: ARM64 SVE format encodings, SVE_BI_2A to SVE_HF_2A #98784
• SVE_BL_1A Add Arm64 encoding for IF_SVE_BL_1A #97223
• SVE_BM_1A JIT ARM64-SVE: Add AW_2A to AZ_2A, BM_1A, BN_1A #99211
• SVE_BN_1A JIT ARM64-SVE: Add AW_2A to AZ_2A, BM_1A, BN_1A #99211
• SVE_BP_1A JIT ARM64-SVE: Add BP_1A to BQ_2B, BU_2A #99245
• SVE_BO_1A JIT ARM64-SVE: Add BP_1A to BQ_2B, BU_2A #99245
• SVE_BO_1A_A JIT ARM64-SVE: Add BP_1A to BQ_2B, BU_2A #99245
• SVE_BQ_2A JIT ARM64-SVE: Add BP_1A to BQ_2B, BU_2A #99245
• SVE_BQ_2B JIT ARM64-SVE: Add BP_1A to BQ_2B, BU_2A #99245
• SVE_BS_1A JIT ARM64-SVE: Add BS_1A, BT_1A #99458
• SVE_BT_1A JIT ARM64-SVE: Add BS_1A, BT_1A #99458
• SVE_BU_2A JIT ARM64-SVE: Add BP_1A to BQ_2B, BU_2A #99245
• SVE_BV_2A ARM64-SVE: Implement IF_SVE_BV_2A #99049
• SVE_BV_2A_A ARM64-SVE: Implement IF_SVE_BV_2A #99049
• SVE_BV_2A_J ARM64-SVE: Implement IF_SVE_BV_2A #99049
• SVE_BV_2B JIT ARM64-SVE: Add BV_2B #99534
• SVE_BW_2A Add ARM64 encodings for group IF_SVE_BW_2A #99411
• SVE_BX_2A - JIT: ARM64 SVE format encodings, SVE_BX_2A and SVE_BY_2A #99087
• SVE_BY_2A - JIT: ARM64 SVE format encodings, SVE_BX_2A and SVE_BY_2A #99087
• SVE_CC_2A - Add ARM64 encodings for group IF_SVE_CC,CD #99284
• SVE_CD_2A - Add ARM64 encodings for group IF_SVE_CC,CD #99284
• SVE_CE_2A - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CE_2B - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CE_2C - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CE_2D - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CF_2A - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CF_2B - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CF_2C - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CF_2D - Add ARM64 encodings for groups IF_SVE_CE,CF #98409
• SVE_CI_3A Add ARM encoding group IF_SVE_CI_3A #97808
• SVE_CJ_2A Add encoding for ARM64 IF_SVE_CJ_2A instruction group #97885
• SVE_CK_2A Add ARM64 encoding for group IF_SVE_CK_2A #97887
• SVE_CT_3A Add ARM64 encodings for group IF_SVE_CT_3A #98085
• SVE_GQ_3A Add ARM64 encodings for group IF_SVE_GQ_3A #98352
• SVE_HO_3A Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HO_3A_B Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HP_3B Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HP_3B_H Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HP_3B_I Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HP_3B_J Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HS_3A Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HS_3A_H Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HS_3A_I Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_HS_3A_J Add ARM64 encodings for groups IF_SVE_HO,HP,HS #99058
• SVE_CV_3A Add Arm64 encoding for groups IF_SVE_CV_3A and IF_SVE_CV_3B #97886
• SVE_CV_3B Add Arm64 encoding for groups IF_SVE_CV_3A and IF_SVE_CV_3B #97886
• SVE_CW_4A Add Arm64 encoding for groups IF_SVE_CW_4A #98762
• SVE_CX_4A Add Arm64 encodings for IF_SVE_CX_4A group #95918
• SVE_CX_4A_A Add Arm64 encodings for SVE IF_SVE_CX_4A_A to IF_SVE_HT_4A group #96214
• SVE_GE_4A Add Arm64 encodings for SVE IF_SVE_CX_4A_A to IF_SVE_HT_4A group #96214
• SVE_HT_4A Add Arm64 encodings for SVE IF_SVE_CX_4A_A to IF_SVE_HT_4A group #96214
• SVE_CY_3A Add Arm64 encodings for IF_SVE_CY_3A and IF_SVE_CY_3B group #96992
• SVE_CY_3B Add Arm64 encodings for IF_SVE_CY_3A and IF_SVE_CY_3B group #96992
• SVE_CZ_4A Add Arm64 encodings for IF_SVE_CZ_4A to IF_SVE_CZ_4A_L group #97393
• SVE_CZ_4A_A Add Arm64 encodings for IF_SVE_CZ_4A to IF_SVE_CZ_4A_L group #97393
• SVE_CZ_4A_K Add Arm64 encodings for IF_SVE_CZ_4A to IF_SVE_CZ_4A_L group #97393
• SVE_CZ_4A_L Add Arm64 encodings for IF_SVE_CZ_4A to IF_SVE_CZ_4A_L group #97393
• SVE_DA_4A Add Arm64 encodings for IF_SVE_DA_4A to IF_SVE_DC_3A group #97645
• SVE_DB_3A Add Arm64 encodings for IF_SVE_DA_4A to IF_SVE_DC_3A group #97645
• SVE_DB_3B Add Arm64 encodings for IF_SVE_DA_4A to IF_SVE_DC_3A group #97645
• SVE_DC_3A Add Arm64 encodings for IF_SVE_DA_4A to IF_SVE_DC_3A group #97645
• SVE_DD_2A Add Arm64 encodings for SVE_DD_2A & SVE_DG_2A #97446
• SVE_DG_2A Add Arm64 encodings for SVE_DD_2A & SVE_DG_2A #97446
• SVE_DE_1A Add Arm64 encoding for IF_SVE_DE_1A group #97557
• SVE_DF_2A Add Arm64 encoding for group SVE_DF_2A to SVE_DK_3A #97774
• SVE_DH_1A Add Arm64 encoding for group SVE_DF_2A to SVE_DK_3A #97774
• SVE_DJ_1A Add Arm64 encoding for group SVE_DF_2A to SVE_DK_3A #97774
• SVE_DI_2A Add Arm64 encoding for group SVE_DF_2A to SVE_DK_3A #97774
• SVE_DK_3A Add Arm64 encoding for group SVE_DF_2A to SVE_DK_3A #97774

Aman Khalid (@amanasifkhalid)

Unique entries= 30, Total formats= 73

• SVE_DL_2A - ARM64-SVE: Implement IF_SVE_DL_2A, IF_SVE_DZ_1A, IF_SVE_EA_1A #97068
• SVE_DM_2A - JIT ARM64/SVE2: Add increment/decrement from predicate register instructions #94811
• SVE_DN_2A - JIT ARM64/SVE2: Add increment/decrement from predicate register instructions #94811
• SVE_DP_2A - JIT ARM64/SVE2: Add increment/decrement from predicate register instructions #94811
• SVE_DO_2A - JIT ARM64/SVE2: Add increment/decrement from predicate register instructions #94811
• SVE_DO_2A_A - JIT ARM64/SVE2: Add increment/decrement from predicate register instructions #94811
• SVE_DQ_0A - JIT ARM64-SVE2: Add IF_SVE_DQ_0A, IF_SVE_DR_1A, IF_SVE_DS_2A #95996
• SVE_DR_1A - JIT ARM64-SVE2: Add IF_SVE_DQ_0A, IF_SVE_DR_1A, IF_SVE_DS_2A #95996
• SVE_DS_2A - JIT ARM64-SVE2: Add IF_SVE_DQ_0A, IF_SVE_DR_1A, IF_SVE_DS_2A #95996
• SVE_DT_3A - JIT ARM64: Add IF_SVE_DT_3A, IF_SVE_DU_3A, IF_SVE_DX_3A, IF_SVE_DY_3A #96201
• SVE_DU_3A - JIT ARM64: Add IF_SVE_DT_3A, IF_SVE_DU_3A, IF_SVE_DX_3A, IF_SVE_DY_3A #96201
• SVE_DV_4A - JIT ARM64 SVE: Add FZ_2A, HG_2A, GZ_3A, GV_3A, GY_3*, DV_4A #98310
• SVE_DW_2A - ARM64-SVE: Implement IF_SVE_DW_2A, IF_SVE_DW_2B, IF_SVE_EB_1B #97800
• SVE_DW_2B - ARM64-SVE: Implement IF_SVE_DW_2A, IF_SVE_DW_2B, IF_SVE_EB_1B #97800
• SVE_DX_3A - JIT ARM64: Add IF_SVE_DT_3A, IF_SVE_DU_3A, IF_SVE_DX_3A, IF_SVE_DY_3A #96201
• SVE_DY_3A - JIT ARM64: Add IF_SVE_DT_3A, IF_SVE_DU_3A, IF_SVE_DX_3A, IF_SVE_DY_3A #96201
• SVE_DZ_1A - ARM64-SVE: Implement IF_SVE_DL_2A, IF_SVE_DZ_1A, IF_SVE_EA_1A #97068
• SVE_EA_1A - ARM64-SVE: Implement IF_SVE_DL_2A, IF_SVE_DZ_1A, IF_SVE_EA_1A #97068
• SVE_ED_1A - ARM64-SVE: Implement IF_SVE_ED_1A, IF_SVE_EE_1A, IF_SVE_EB_1A, IF_SVE_EC_1A #97238
• SVE_EE_1A - ARM64-SVE: Implement IF_SVE_ED_1A, IF_SVE_EE_1A, IF_SVE_EB_1A, IF_SVE_EC_1A #97238
• SVE_EB_1A - ARM64-SVE: Implement IF_SVE_ED_1A, IF_SVE_EE_1A, IF_SVE_EB_1A, IF_SVE_EC_1A #97238
• SVE_EC_1A - ARM64-SVE: Implement IF_SVE_ED_1A, IF_SVE_EE_1A, IF_SVE_EB_1A, IF_SVE_EC_1A #97238
• SVE_EB_1B - ARM64-SVE: Implement IF_SVE_DW_2A, IF_SVE_DW_2B, IF_SVE_EB_1B #97800
• SVE_EG_3A - JIT ARM64-SVE: Implement IF_SVE_EG_3A, IF_SVE_EY_3A, IF_SVE_EZ_3A #97900
• SVE_EY_3A - JIT ARM64-SVE: Implement IF_SVE_EG_3A, IF_SVE_EY_3A, IF_SVE_EZ_3A #97900
• SVE_EZ_3A - JIT ARM64-SVE: Implement IF_SVE_EG_3A, IF_SVE_EY_3A, IF_SVE_EZ_3A #97900
• SVE_FD_3B - JIT ARM64-SVE: Implement IF_SVE_FD_3A, IF_SVE_FD_3B, IF_SVE_FD_3C #97934
• SVE_FF_3B - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_FI_3B - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FK_3B - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_GU_3A - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_GX_3A - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_GY_3B - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_GY_3B_D - JIT ARM64 SVE: Add FZ_2A, HG_2A, GZ_3A, GV_3A, GY_3*, DV_4A #98310
• SVE_EJ_3A - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_EK_3A - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_EW_3B - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_EY_3B - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_FD_3C - JIT ARM64-SVE: Implement IF_SVE_FD_3A, IF_SVE_FD_3B, IF_SVE_FD_3C #97934
• SVE_FF_3C - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_FI_3C - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FK_3C - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_GU_3B - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_GX_3B - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_FA_3A - JIT ARM64-SVE: Implement IF_SVE_F{A,B,C}_3{A,B} #97933
• SVE_FB_3A - JIT ARM64-SVE: Implement IF_SVE_F{A,B,C}_3{A,B} #97933
• SVE_FC_3A - JIT ARM64-SVE: Implement IF_SVE_F{A,B,C}_3{A,B} #97933
• SVE_FA_3B - JIT ARM64-SVE: Implement IF_SVE_F{A,B,C}_3{A,B} #97933
• SVE_FB_3B - JIT ARM64-SVE: Implement IF_SVE_F{A,B,C}_3{A,B} #97933
• SVE_FC_3B - JIT ARM64-SVE: Implement IF_SVE_F{A,B,C}_3{A,B} #97933
• SVE_GV_3A - JIT ARM64 SVE: Add FZ_2A, HG_2A, GZ_3A, GV_3A, GY_3*, DV_4A #98310
• SVE_FD_3A - JIT ARM64-SVE: Implement IF_SVE_FD_3A, IF_SVE_FD_3B, IF_SVE_FD_3C #97934
• SVE_FF_3A - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_FI_3A - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FK_3A - JIT ARM64-SVE: Add FK_3{A,B,C}, EJ_3A, EK_3A, EY_3B, EW_3{A,B} #98187
• SVE_GU_3C - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_GX_3C - JIT ARM64-SVE: Add IF_SVE_GU_3*, IF_SVE_GX_3*, IF_SVE_FF_3*, IF_SVE_GY_3B #98136
• SVE_FE_3A - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FG_3A - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FH_3A - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FJ_3A - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_GY_3A - JIT ARM64 SVE: Add FZ_2A, HG_2A, GZ_3A, GV_3A, GY_3*, DV_4A #98310
• SVE_GZ_3A - JIT ARM64 SVE: Add FZ_2A, HG_2A, GZ_3A, GV_3A, GY_3*, DV_4A #98310
• SVE_FE_3B - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FG_3B - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FH_3B - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FJ_3B - JIT ARM64-SVE: Add IF_SVE_F{E,G,H,I,J}_3* #98142
• SVE_FR_2A - JIT ARM64-SVE: Add FR_2A, GB_2A, FV_2A, FY_3A #98248
• SVE_GB_2A - JIT ARM64-SVE: Add FR_2A, GB_2A, FV_2A, FY_3A #98248
• SVE_FV_2A - JIT ARM64-SVE: Add FR_2A, GB_2A, FV_2A, FY_3A #98248
• SVE_FY_3A - JIT ARM64-SVE: Add FR_2A, GB_2A, FV_2A, FY_3A #98248
• SVE_FZ_2A - JIT ARM64 SVE: Add FZ_2A, HG_2A, GZ_3A, GV_3A, GY_3*, DV_4A #98310
• SVE_HG_2A - JIT ARM64 SVE: Add FZ_2A, HG_2A, GZ_3A, GV_3A, GY_3*, DV_4A #98310

Will Smith (@TIHan)

Unique entries= 32, Total formats= 113

• SVE_GA_2A - JIT: Added ARM64 SVE_GA_2A encoding #95435
• SVE_GD_2A - JIT: Added SVE_GD_2A ARM64 encoding #95618
• SVE_GG_3A - JIT: ARM64 SVE format encodings, SVE_GG_3A to SVE_GH_3A #98316
• SVE_GH_3B - JIT: ARM64 SVE format encodings, SVE_GG_3A to SVE_GH_3A #98316
• SVE_GH_3B_B - JIT: ARM64 SVE format encodings, SVE_GG_3A to SVE_GH_3A #98316
• SVE_GG_3B - JIT: ARM64 SVE format encodings, SVE_GG_3A to SVE_GH_3A #98316
• SVE_GH_3A - JIT: ARM64 SVE format encodings, SVE_GG_3A to SVE_GH_3A #98316
• SVE_GK_2A - JIT: Added SVE_GK_2A and SVE_GL_1A arm64 encodings #95707
• SVE_GL_1A - JIT: Added SVE_GK_2A and SVE_GL_1A arm64 encodings #95707
• SVE_GM_3A - (awaiting capstone update to verify - see ARM64: Unable to decode fmlalb, fmlalt, fmlallbb, fmlallbt, fmlalltb, fmlalltt instructions capstone-engine/capstone#2270)
• SVE_HC_3A - (awaiting capstone update to verify - see ARM64: Unable to decode fmlalb, fmlalt, fmlallbb, fmlallbt, fmlalltb, fmlalltt instructions capstone-engine/capstone#2270)
• SVE_GP_3A - JIT: ARM64 SVE format encodings, SVE_GP_3A to SVE_HV_4A #98141
• SVE_HI_3A - JIT: ARM64 SVE format encodings, SVE_GP_3A to SVE_HV_4A #98141
• SVE_HM_2A - JIT: ARM64 SVE format encodings, SVE_GP_3A to SVE_HV_4A #98141
• SVE_HN_2A - JIT: ARM64 SVE format encodings, SVE_GP_3A to SVE_HV_4A #98141
• SVE_HP_3A - JIT: ARM64 SVE format encodings, SVE_GP_3A to SVE_HV_4A #98141
• SVE_HU_4B - JIT: ARM64 SVE format encodings, SVE_GP_3A to SVE_HV_4A #98141
• SVE_HV_4A - JIT: ARM64 SVE format encodings, SVE_GP_3A to SVE_HV_4A #98141
• SVE_HW_4A - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_HW_4A_A - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_HW_4A_B - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_HW_4A_C - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_IU_4A - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_IU_4A_A - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_IU_4A_C - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_HW_4B - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_HW_4B_D - JIT: ARM64 SVE format encodings, SVE_HW_4A to SVE_HW_4B_D #97433
• SVE_IF_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IF_4A_A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IG_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IG_4A_D - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IG_4A_E - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IG_4A_F - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IG_4A_G - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_II_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_II_4A_B - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_II_4A_H - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IK_4A_F - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IK_4A_G - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IK_4A_I - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IN_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IP_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IR_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IT_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IU_4B - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IU_4B_B - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IU_4B_D - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IW_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IX_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IY_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IZ_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_IZ_4A_A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JA_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JB_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JC_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JD_4C - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JD_4C_A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JF_4A - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JJ_4B - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JJ_4B_C - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JJ_4B_E - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_JK_4B - JIT: ARM64 SVE format encodings, SVE_IF_4A to SVE_JK_4B #97739
• SVE_HX_3A_B - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_HX_3A_E - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_IV_3A - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_JI_3A_A - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_JL_3A - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_HY_3A - JIT: ARM64 SVE format encodings, SVE_HY_3A to SVE_IB_3A #98468
• SVE_HY_3A_A - JIT: ARM64 SVE format encodings, SVE_HY_3A to SVE_IB_3A #98468
• SVE_HY_3B - JIT: ARM64 SVE format encodings, SVE_HY_3A to SVE_IB_3A #98468
• SVE_IB_3A - JIT: ARM64 SVE format encodings, SVE_HY_3A to SVE_IB_3A #98468
• SVE_HZ_2A_B - JIT: ARM64 SVE format encodings, SVE_HY_3A to SVE_IB_3A #98468
• SVE_IA_2A - JIT: ARM64 SVE format encodings, SVE_HY_3A to SVE_IB_3A #98468
• SVE_IC_3A - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_IC_3A_A - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_IC_3A_B - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_IC_3A_C - JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332
• SVE_ID_2A - JIT: ARM64 SVE format encodings, SVE_ID_2A to SVE_JH_2A #98015
• SVE_JG_2A - JIT: ARM64 SVE format encodings, SVE_ID_2A to SVE_JH_2A #98015
• SVE_IE_2A - JIT: ARM64 SVE format encodings, SVE_ID_2A to SVE_JH_2A #98015
• SVE_JH_2A - JIT: ARM64 SVE format encodings, SVE_ID_2A to SVE_JH_2A #98015
• SVE_IH_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IH_3A_A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IH_3A_F - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IJ_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IJ_3A_D - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IJ_3A_E - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IJ_3A_F - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IJ_3A_G - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IL_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IL_3A_A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IL_3A_B - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IL_3A_C - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IM_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IO_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IQ_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_IS_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_JE_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_JM_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_JN_3C - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_JN_3C_D - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_JO_3A - JIT: ARM64 SVE format encodings, SVE_IH_3A to SVE_JO_3A #95994
• SVE_JD_4A - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JD_4B - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JJ_4A - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JJ_4A_B - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JJ_4A_C - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JJ_4A_D - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JK_4A - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JK_4A_B - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JN_3A - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129
• SVE_JN_3B - JIT: ARM64 SVE format encodings, SVE_JD_4A to SVE_JN_3B #97129

PS: Unique entries means number of implementation the person has to write for their assignment. Total entries means number for format names they will cover.

[kunalspathak]

cc: @dotnet/jit-contrib , @BruceForstall

Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch
See info in area-owners.md if you want to be subscribed.

Issue Details

---

Summary

Based upon the model I prototyped in #94529, let us try to use the boiler plate code that the tool generated to implement following methods.

• emitOutputInstr()
• emitInsDispHelp()
• emitInsSanityCheck
• genAmd64EmitterUnitTests()
• getInsExecutionCharacteristics()

I have split the implementation among Alan, Alan and Will. I will join the efforts once I get am done with register allocation support for predicate registers. Once I do some cleanup to the tool, I will share the repo of the tool so you can generate the boiler plate files on your own.

PR expectation

We need to still figure out the encoding validation story, but that or the pending register allocation work should not stop us to start implementing these formats. The PRs should be small enough that implements all the methods listed above for the group of format names.

Assignments

Alan Hayward (@a74nh)

Unique entries= 61, Total formats= 163

• SVE_AA_3A
• SVE_AB_3A
• SVE_AC_3A
• SVE_AD_3A
• SVE_AE_3A
• SVE_AN_3A
• SVE_AO_3A
• SVE_CM_3A
• SVE_CN_3A
• SVE_CO_3A
• SVE_EP_3A
• SVE_ER_3A
• SVE_ET_3A
• SVE_EU_3A
• SVE_GR_3A
• SVE_HJ_3A
• SVE_HL_3A
• SVE_AB_3B
• SVE_HL_3B
• SVE_AF_3A
• SVE_AG_3A
• SVE_AI_3A
• SVE_AJ_3A
• SVE_AK_3A
• SVE_AL_3A
• SVE_AP_3A
• SVE_AQ_3A
• SVE_CL_3A
• SVE_CP_3A
• SVE_CQ_3A
• SVE_CR_3A
• SVE_CS_3A
• SVE_CU_3A
• SVE_EQ_3A
• SVE_ES_3A
• SVE_GS_3A
• SVE_HE_3A
• SVE_HQ_3A
• SVE_HR_3A
• SVE_AH_3A
• SVE_AM_2A
• SVE_AR_4A
• SVE_GI_4A
• SVE_HU_4A
• SVE_AS_4A
• SVE_AT_3A
• SVE_BA_3A
• SVE_BD_3A
• SVE_BE_3A
• SVE_BG_3A
• SVE_BK_3A
• SVE_BR_3A
• SVE_BZ_3A
• SVE_CA_3A
• SVE_EH_3A
• SVE_EL_3A
• SVE_EM_3A
• SVE_EN_3A
• SVE_EO_3A
• SVE_EV_3A
• SVE_EX_3A
• SVE_FL_3A
• SVE_FM_3A
• SVE_FN_3A
• SVE_FP_3A
• SVE_FQ_3A
• SVE_FS_3A
• SVE_FW_3A
• SVE_FX_3A
• SVE_GC_3A
• SVE_GF_3A
• SVE_GW_3A
• SVE_HK_3A
• SVE_AT_3B
• SVE_AU_3A
• SVE_BD_3B
• SVE_BR_3B
• SVE_EF_3A
• SVE_EI_3A
• SVE_EW_3A
• SVE_FN_3B
• SVE_FO_3A
• SVE_GJ_3A
• SVE_GN_3A
• SVE_GO_3A
• SVE_GW_3B
• SVE_HA_3A
• SVE_HB_3A
• SVE_HD_3A
• SVE_HK_3B
• SVE_AV_3A
• SVE_AW_2A
• SVE_AX_1A
• SVE_AY_2A
• SVE_AZ_2A
• SVE_BB_2A
• SVE_BC_1A
• SVE_BF_2A
• SVE_FT_2A
• SVE_FU_2A
• SVE_BH_3A
• SVE_BH_3B
• SVE_BI_2A
• SVE_HH_2A
• SVE_BJ_2A
• SVE_CB_2A
• SVE_CG_2A
• SVE_CH_2A
• SVE_HF_2A
• SVE_BL_1A
• SVE_BM_1A
• SVE_BN_1A
• SVE_BP_1A
• SVE_BO_1A
• SVE_BQ_2A
• SVE_BQ_2B
• SVE_BS_1A
• SVE_BT_1A
• SVE_BU_2A
• SVE_BV_2A
• SVE_BV_2B
• SVE_BW_2A
• SVE_BX_2A
• SVE_BY_2A
• SVE_CC_2A
• SVE_CD_2A
• SVE_CE_2A
• SVE_CE_2B
• SVE_CE_2C
• SVE_CE_2D
• SVE_CF_2A
• SVE_CF_2B
• SVE_CF_2C
• SVE_CF_2D
• SVE_CI_3A
• SVE_CJ_2A
• SVE_CK_2A
• SVE_CT_3A
• SVE_GQ_3A
• SVE_HO_3A
• SVE_HP_3B
• SVE_HS_3A
• SVE_CV_3A
• SVE_CV_3B
• SVE_CW_4A
• SVE_CX_4A
• SVE_GE_4A
• SVE_HT_4A
• SVE_CY_3A
• SVE_CY_3B
• SVE_CZ_4A
• SVE_DA_4A
• SVE_DB_3A
• SVE_DB_3B
• SVE_DC_3A
• SVE_DD_2A
• SVE_DG_2A
• SVE_DE_1A
• SVE_DF_2A
• SVE_DH_1A
• SVE_DJ_1A
• SVE_DI_2A
• SVE_DK_3A

Aman Khalid (@amanasifkhalid)

Unique entries= 30, Total formats= 71

• SVE_DL_2A
• SVE_DM_2A
• SVE_DN_2A
• SVE_DP_2A
• SVE_DO_2A
• SVE_DQ_0A
• SVE_DR_1A
• SVE_DS_2A
• SVE_DT_3A
• SVE_DU_3A
• SVE_DV_4A
• SVE_DW_2A
• SVE_DW_2B
• SVE_DX_3A
• SVE_DY_3A
• SVE_DZ_1A
• SVE_EA_1A
• SVE_ED_1A
• SVE_EE_1A
• SVE_EB_1A
• SVE_EC_1A
• SVE_EB_1B
• SVE_EG_3A
• SVE_EY_3A
• SVE_EZ_3A
• SVE_FD_3B
• SVE_FF_3B
• SVE_FI_3B
• SVE_FK_3B
• SVE_GU_3A
• SVE_GX_3A
• SVE_GY_3B
• SVE_EJ_3A
• SVE_EK_3A
• SVE_EW_3B
• SVE_EY_3B
• SVE_FD_3C
• SVE_FF_3C
• SVE_FI_3C
• SVE_FK_3C
• SVE_GU_3B
• SVE_GX_3B
• SVE_FA_3A
• SVE_FB_3A
• SVE_FC_3A
• SVE_FA_3B
• SVE_FB_3B
• SVE_FC_3B
• SVE_GV_3A
• SVE_FD_3A
• SVE_FF_3A
• SVE_FI_3A
• SVE_FK_3A
• SVE_GU_3C
• SVE_GX_3C
• SVE_FE_3A
• SVE_FG_3A
• SVE_FH_3A
• SVE_FJ_3A
• SVE_GY_3A
• SVE_GZ_3A
• SVE_FE_3B
• SVE_FG_3B
• SVE_FH_3B
• SVE_FJ_3B
• SVE_FR_2A
• SVE_GB_2A
• SVE_FV_2A
• SVE_FY_3A
• SVE_FZ_2A
• SVE_HG_2A

Will Smith (@TIHan)

Unique entries= 32, Total formats= 72

• SVE_GA_2A
• SVE_GD_2A
• SVE_GG_3A
• SVE_GH_3B
• SVE_GG_3B
• SVE_GH_3A
• SVE_GK_2A
• SVE_GL_1A
• SVE_GM_3A
• SVE_HC_3A
• SVE_GP_3A
• SVE_GT_4A
• SVE_HI_3A
• SVE_HM_2A
• SVE_HN_2A
• SVE_HP_3A
• SVE_HU_4B
• SVE_HV_4A
• SVE_HW_4A
• SVE_IU_4A
• SVE_HW_4B
• SVE_IF_4A
• SVE_IG_4A
• SVE_II_4A
• SVE_IK_4A
• SVE_IN_4A
• SVE_IP_4A
• SVE_IR_4A
• SVE_IT_4A
• SVE_IU_4B
• SVE_IW_4A
• SVE_IX_4A
• SVE_IY_4A
• SVE_IZ_4A
• SVE_JA_4A
• SVE_JB_4A
• SVE_JC_4A
• SVE_JD_4C
• SVE_JF_4A
• SVE_JJ_4B
• SVE_JK_4B
• SVE_HX_3A
• SVE_IV_3A
• SVE_JI_3A
• SVE_JL_3A
• SVE_HY_3A
• SVE_HY_3B
• SVE_IB_3A
• SVE_HZ_2A
• SVE_IA_2A
• SVE_IC_3A
• SVE_ID_2A
• SVE_JG_2A
• SVE_IE_2A
• SVE_JH_2A
• SVE_IH_3A
• SVE_IJ_3A
• SVE_IL_3A
• SVE_IM_3A
• SVE_IO_3A
• SVE_IQ_3A
• SVE_IS_3A
• SVE_JE_3A
• SVE_JM_3A
• SVE_JN_3C
• SVE_JO_3A
• SVE_JD_4A
• SVE_JD_4B
• SVE_JJ_4A
• SVE_JK_4A
• SVE_JN_3A
• SVE_JN_3B

PS: Unique entries means number of implementation the person has to write for their assignment. Total entries means number for format names they will cover.

Contributes to #93095

Author:	kunalspathak
Assignees:	-
Labels:	area-CodeGen-coreclr, untriaged, needs-area-label
Milestone:	-

[a74nh]

• genAmd64EmitterUnitTests()
• getInsExecutionCharacteristics()

Link text is wrong.

Not sure how many of these are fixable in the script and which ones are intentional we should be manually fixing up

emitInsSanityCheck_sve.cpp.txt

• id->idReg10() instead of id->idReg1(), etc for idReg20, idReg30...
• Uses of isVectorRegister() should be isSveRegister()
• The predicate is always the last register (eg idReg30). I think the predicate should be the first argument after the destination register to match the assembly printing order and the API args order (eg idReg2).

emitDispInsHelp_sve.cpp.txt

• Same idReg10 etc
• And uses of emitDispVectorReg instead of emitDispSveReg

emitArm64EmitterUnitTests_sve.cpp.txt

• Could you add the group name onto the end of the line. eg:

theEmitter->emitIns_R_R_R(INS_sve_add, EA_8BYTE, REG_R0, REG_R1, REG_R2, INS_OPTS_8B);  // ADD     <Zdn>.<T>, <Pg>/M, <Zdn>.<T>, <Zm>.<T>   IF_SVE_AB_3A

This way it's much easier to find all the lines required for a given group.
For example, currently I'm adding everything for group IF_SVE_AB_3A. I have find all the matches in instrarm64sve.h, then find each of those in emitArm64EmitterUnitTests_sve

[kunalspathak]

id->idReg10() instead of id->idReg1(), etc for idReg20, idReg30...

This was done intentionally, so the developers fix them by hand while making sure that they are correct.

isVectorRegister() should be isSveRegister()
emitDispVectorReg instead of emitDispSveReg

Yes, this can be fixed.

add the group name onto the end of the line.

Sure.

The predicate is always the last register (eg idReg30). I think the predicate should be the first argument after the destination register to match the assembly printing order and the API args order (eg idReg2).

Thanks for spotting that. Let me double check.

Also as I pointed in #94811 (comment), I will see if I can differentiate REF_V1 (vector register) vs. REG_R1 (gpr) in emitArm64EmitterUnitTests_sve.cpp.txt.

[kunalspathak]

isVectorRegister() should be isSveRegister()

I think this should be same because they are same register files. I have update the sanitycheck to also check for INS_OPTS_SCALABLE_*`.

emitDispVectorReg instead of emitDispSveReg

Done.

add the group name onto the end of the line.

Done.

The predicate is always the last register (eg idReg30).

That's not the case. I go from LSB to MSB and use idReg0, idReg1, etc. in that order. Below, you see ggg populated with idReg3 and then with idReg2. It actually doesn't matter what order we encode because the bits will anyway be placed at right position in insEncodeReg_* methods.

case IF_SVE_HI_3A:   // ........xx...... ...gggnnnnn.DDDD -- SVE floating-point compare with zero
   code = emitInsCodeSve(ins, fmt);
   elemsize = id->idOpSize();
   code |= insEncodeReg_Pd(id->idReg10()); // DDDD
   code |= insEncodeReg_Vn(id->idReg20()); // nnnnn
   code |= insEncodeReg_Pg(id->idReg30()); // ggg
   code |= insEncodeElemsize(elemsize); // xx
   dst += emitOutput_Instr(dst, code);
   break;

case IF_SVE_IB_3A:   // ...........mmmmm ...gggnnnnn.oooo -- SVE contiguous prefetch (scalar plus scalar)
   code = emitInsCodeSve(ins, fmt);
   code |= insEncodePrfop(); // oooo
   code |= insEncodeReg_Rn(id->idReg10()); // nnnnn
   code |= insEncodeReg_Pg(id->idReg20()); // ggg
   code |= insEncodeReg_Vm(id->idReg30()); // mmmmm
   dst += emitOutput_Instr(dst, code);
   break;