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JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332

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Merged
merged 13 commits into from
Feb 16, 2024
Merged

JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C #98332

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e385de6
Initial format boilerplate
TIHan Feb 12, 2024
7445edf
SVE_HX_3A_B format working
TIHan Feb 12, 2024
5b53fee
SVE_HX_3A_E working
TIHan Feb 12, 2024
e9a27d3
SVE_IV_3A working
TIHan Feb 12, 2024
98b3b34
SVE_JI_3A_A and SVE_JL_3A working
TIHan Feb 12, 2024
4bc1483
SVE_IC_3A working
TIHan Feb 12, 2024
2863c7f
cleanup
TIHan Feb 12, 2024
3b180b2
SVE_IC_3A_A working
TIHan Feb 12, 2024
38d51a1
Finishing up
TIHan Feb 13, 2024
bda779e
remove case
TIHan Feb 13, 2024
c6782db
Merged with main
TIHan Feb 15, 2024
147605e
Fix build. Added emitInsSve_R_R_R_I
TIHan Feb 15, 2024
d04f8c6
Formatting
TIHan Feb 16, 2024
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126 changes: 126 additions & 0 deletions src/coreclr/jit/codegenarm64test.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -7598,6 +7598,132 @@ void CodeGen::genArm64EmitterUnitTestsSve()
INS_SCALABLE_OPTS_UNPREDICATED);
theEmitter->emitIns_R_R_I(INS_sve_str, EA_SCALABLE, REG_V2, REG_R3, 255, INS_OPTS_NONE,
INS_SCALABLE_OPTS_UNPREDICATED);

// IF_SVE_HX_3A_B
theEmitter->emitIns_R_R_R_I(INS_sve_ld1b, EA_SCALABLE, REG_V0, REG_P0, REG_V1, 0,
INS_OPTS_SCALABLE_S); // LD1B {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sb, EA_SCALABLE, REG_V2, REG_P7, REG_V3, 5,
INS_OPTS_SCALABLE_S); // LD1SB {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1b, EA_SCALABLE, REG_V4, REG_P3, REG_V1, 5,
INS_OPTS_SCALABLE_S); // LDFF1B {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sb, EA_SCALABLE, REG_V2, REG_P6, REG_V0, 31,
INS_OPTS_SCALABLE_S); // LDFF1SB {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1b, EA_SCALABLE, REG_V0, REG_P0, REG_V1, 0,
INS_OPTS_SCALABLE_D); // LD1B {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sb, EA_SCALABLE, REG_V2, REG_P7, REG_V3, 5,
INS_OPTS_SCALABLE_D); // LD1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1b, EA_SCALABLE, REG_V4, REG_P3, REG_V1, 5,
INS_OPTS_SCALABLE_D); // LDFF1B {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sb, EA_SCALABLE, REG_V2, REG_P6, REG_V0, 31,
INS_OPTS_SCALABLE_D); // LDFF1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]

// IF_SVE_HX_3A_E
theEmitter->emitIns_R_R_R_I(INS_sve_ld1h, EA_SCALABLE, REG_V1, REG_P0, REG_V2, 0,
INS_OPTS_SCALABLE_S); // LD1H {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sh, EA_SCALABLE, REG_V2, REG_P4, REG_V3, 2,
INS_OPTS_SCALABLE_S); // LD1SH {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1w, EA_SCALABLE, REG_V1, REG_P2, REG_V9, 124,
INS_OPTS_SCALABLE_S); // LD1W {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1h, EA_SCALABLE, REG_V4, REG_P7, REG_V3, 6,
INS_OPTS_SCALABLE_S); // LDFF1H {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sh, EA_SCALABLE, REG_V3, REG_P5, REG_V4, 62,
INS_OPTS_SCALABLE_S); // LDFF1SH {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1w, EA_SCALABLE, REG_V2, REG_P1, REG_V3, 124,
INS_OPTS_SCALABLE_S); // LDFF1W {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1h, EA_SCALABLE, REG_V1, REG_P0, REG_V2, 0,
INS_OPTS_SCALABLE_D); // LD1H {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sh, EA_SCALABLE, REG_V2, REG_P4, REG_V3, 2,
INS_OPTS_SCALABLE_D); // LD1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1w, EA_SCALABLE, REG_V1, REG_P2, REG_V9, 124,
INS_OPTS_SCALABLE_D); // LD1W {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1h, EA_SCALABLE, REG_V4, REG_P7, REG_V3, 6,
INS_OPTS_SCALABLE_D); // LDFF1H {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sh, EA_SCALABLE, REG_V3, REG_P5, REG_V4, 62,
INS_OPTS_SCALABLE_D); // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1w, EA_SCALABLE, REG_V2, REG_P1, REG_V3, 124,
INS_OPTS_SCALABLE_D); // LDFF1W {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]

// IF_SVE_IV_3A
theEmitter->emitIns_R_R_R_I(INS_sve_ld1d, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 0,
INS_OPTS_SCALABLE_D); // LD1D {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sw, EA_SCALABLE, REG_V6, REG_P5, REG_V4, 0,
INS_OPTS_SCALABLE_D); // LD1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1d, EA_SCALABLE, REG_V7, REG_P3, REG_V1, 248,
INS_OPTS_SCALABLE_D); // LDFF1D {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sw, EA_SCALABLE, REG_V2, REG_P0, REG_V4, 124,
INS_OPTS_SCALABLE_D); // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]

// IF_SVE_JI_3A_A
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 0,
INS_OPTS_SCALABLE_S); // ST1B {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 31,
INS_OPTS_SCALABLE_S); // ST1B {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 0,
INS_OPTS_SCALABLE_S); // ST1H {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 62,
INS_OPTS_SCALABLE_S); // ST1H {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 0,
INS_OPTS_SCALABLE_S); // ST1W {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 124,
INS_OPTS_SCALABLE_S); // ST1W {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 0,
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 31,
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 0,
INS_OPTS_SCALABLE_D); // ST1H {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 62,
INS_OPTS_SCALABLE_D); // ST1H {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 0,
INS_OPTS_SCALABLE_D); // ST1W {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 124,
INS_OPTS_SCALABLE_D); // ST1W {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]

// IF_SVE_JL_3A
theEmitter->emitIns_R_R_R_I(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P7, REG_V4, 0,
INS_OPTS_SCALABLE_D); // ST1D {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P7, REG_V4, 248,
INS_OPTS_SCALABLE_D); // ST1D {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]

// IF_SVE_IC_3A
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rd, EA_SCALABLE, REG_V1, REG_P2, REG_R3, 504,
INS_OPTS_SCALABLE_D); // LD1RD {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsw, EA_SCALABLE, REG_V4, REG_P5, REG_R6, 252,
INS_OPTS_SCALABLE_D); // LD1RSW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

// IF_SVE_IC_3A_A
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsh, EA_SCALABLE, REG_V0, REG_P1, REG_R2, 0,
INS_OPTS_SCALABLE_S); // LD1RSH {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rw, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 0,
INS_OPTS_SCALABLE_S); // LD1RW {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsh, EA_SCALABLE, REG_V0, REG_P1, REG_R2, 126,
INS_OPTS_SCALABLE_D); // LD1RSH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rw, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 252,
INS_OPTS_SCALABLE_D); // LD1RW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

// IF_SVE_IC_3A_B
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rh, EA_SCALABLE, REG_V0, REG_P2, REG_R3, 0,
INS_OPTS_SCALABLE_H); // LD1RH {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsb, EA_SCALABLE, REG_V6, REG_P5, REG_R4, 0,
INS_OPTS_SCALABLE_H); // LD1RSB {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rh, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 126,
INS_OPTS_SCALABLE_S); // LD1RH {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsb, EA_SCALABLE, REG_V2, REG_P1, REG_R0, 63,
INS_OPTS_SCALABLE_S); // LD1RSB {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rh, EA_SCALABLE, REG_V3, REG_P2, REG_R1, 126,
INS_OPTS_SCALABLE_D); // LD1RH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsb, EA_SCALABLE, REG_V4, REG_P5, REG_R6, 63,
INS_OPTS_SCALABLE_D); // LD1RSB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]

// IF_SVE_IC_3A_C
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V1, REG_P2, REG_R3, 0,
INS_OPTS_SCALABLE_B); // LD1RB {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 63,
INS_OPTS_SCALABLE_H); // LD1RB {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V6, REG_P7, REG_R8, 0,
INS_OPTS_SCALABLE_S); // LD1RB {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V1, REG_P0, REG_R9, 63,
INS_OPTS_SCALABLE_B); // LD1RB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
}

#endif // defined(TARGET_ARM64) && defined(DEBUG)
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