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TIHanTIHan
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JIT: ARM64 SVE format encodings, SVE_HX_3A_B to SVE_JL_3A and SVE_IC_3A to SVE_IC_3A_C (#98332)
* Initial format boilerplate * SVE_HX_3A_B format working * SVE_HX_3A_E working * SVE_IV_3A working * SVE_JI_3A_A and SVE_JL_3A working * SVE_IC_3A working * cleanup * SVE_IC_3A_A working * Finishing up * remove case * Fix build. Added emitInsSve_R_R_R_I * Formatting
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‎src/coreclr/jit/codegenarm64test.cpp

Lines changed: 126 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -7598,6 +7598,132 @@ void CodeGen::genArm64EmitterUnitTestsSve()
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INS_SCALABLE_OPTS_UNPREDICATED);
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theEmitter->emitIns_R_R_I(INS_sve_str, EA_SCALABLE, REG_V2, REG_R3, 255, INS_OPTS_NONE,
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INS_SCALABLE_OPTS_UNPREDICATED);
7601+
7602+
// IF_SVE_HX_3A_B
7603+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1b, EA_SCALABLE, REG_V0, REG_P0, REG_V1, 0,
7604+
INS_OPTS_SCALABLE_S); // LD1B {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7605+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sb, EA_SCALABLE, REG_V2, REG_P7, REG_V3, 5,
7606+
INS_OPTS_SCALABLE_S); // LD1SB {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7607+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1b, EA_SCALABLE, REG_V4, REG_P3, REG_V1, 5,
7608+
INS_OPTS_SCALABLE_S); // LDFF1B {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7609+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sb, EA_SCALABLE, REG_V2, REG_P6, REG_V0, 31,
7610+
INS_OPTS_SCALABLE_S); // LDFF1SB {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7611+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1b, EA_SCALABLE, REG_V0, REG_P0, REG_V1, 0,
7612+
INS_OPTS_SCALABLE_D); // LD1B {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7613+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sb, EA_SCALABLE, REG_V2, REG_P7, REG_V3, 5,
7614+
INS_OPTS_SCALABLE_D); // LD1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7615+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1b, EA_SCALABLE, REG_V4, REG_P3, REG_V1, 5,
7616+
INS_OPTS_SCALABLE_D); // LDFF1B {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7617+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sb, EA_SCALABLE, REG_V2, REG_P6, REG_V0, 31,
7618+
INS_OPTS_SCALABLE_D); // LDFF1SB {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7619+
7620+
// IF_SVE_HX_3A_E
7621+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1h, EA_SCALABLE, REG_V1, REG_P0, REG_V2, 0,
7622+
INS_OPTS_SCALABLE_S); // LD1H {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7623+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sh, EA_SCALABLE, REG_V2, REG_P4, REG_V3, 2,
7624+
INS_OPTS_SCALABLE_S); // LD1SH {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7625+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1w, EA_SCALABLE, REG_V1, REG_P2, REG_V9, 124,
7626+
INS_OPTS_SCALABLE_S); // LD1W {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7627+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1h, EA_SCALABLE, REG_V4, REG_P7, REG_V3, 6,
7628+
INS_OPTS_SCALABLE_S); // LDFF1H {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7629+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sh, EA_SCALABLE, REG_V3, REG_P5, REG_V4, 62,
7630+
INS_OPTS_SCALABLE_S); // LDFF1SH {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7631+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1w, EA_SCALABLE, REG_V2, REG_P1, REG_V3, 124,
7632+
INS_OPTS_SCALABLE_S); // LDFF1W {<Zt>.S }, <Pg>/Z, [<Zn>.S{, #<imm>}]
7633+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1h, EA_SCALABLE, REG_V1, REG_P0, REG_V2, 0,
7634+
INS_OPTS_SCALABLE_D); // LD1H {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7635+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sh, EA_SCALABLE, REG_V2, REG_P4, REG_V3, 2,
7636+
INS_OPTS_SCALABLE_D); // LD1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7637+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1w, EA_SCALABLE, REG_V1, REG_P2, REG_V9, 124,
7638+
INS_OPTS_SCALABLE_D); // LD1W {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7639+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1h, EA_SCALABLE, REG_V4, REG_P7, REG_V3, 6,
7640+
INS_OPTS_SCALABLE_D); // LDFF1H {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7641+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sh, EA_SCALABLE, REG_V3, REG_P5, REG_V4, 62,
7642+
INS_OPTS_SCALABLE_D); // LDFF1SH {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7643+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1w, EA_SCALABLE, REG_V2, REG_P1, REG_V3, 124,
7644+
INS_OPTS_SCALABLE_D); // LDFF1W {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7645+
7646+
// IF_SVE_IV_3A
7647+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1d, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 0,
7648+
INS_OPTS_SCALABLE_D); // LD1D {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7649+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1sw, EA_SCALABLE, REG_V6, REG_P5, REG_V4, 0,
7650+
INS_OPTS_SCALABLE_D); // LD1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7651+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1d, EA_SCALABLE, REG_V7, REG_P3, REG_V1, 248,
7652+
INS_OPTS_SCALABLE_D); // LDFF1D {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7653+
theEmitter->emitIns_R_R_R_I(INS_sve_ldff1sw, EA_SCALABLE, REG_V2, REG_P0, REG_V4, 124,
7654+
INS_OPTS_SCALABLE_D); // LDFF1SW {<Zt>.D }, <Pg>/Z, [<Zn>.D{, #<imm>}]
7655+
7656+
// IF_SVE_JI_3A_A
7657+
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 0,
7658+
INS_OPTS_SCALABLE_S); // ST1B {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
7659+
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 31,
7660+
INS_OPTS_SCALABLE_S); // ST1B {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
7661+
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 0,
7662+
INS_OPTS_SCALABLE_S); // ST1H {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
7663+
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 62,
7664+
INS_OPTS_SCALABLE_S); // ST1H {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
7665+
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 0,
7666+
INS_OPTS_SCALABLE_S); // ST1W {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
7667+
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 124,
7668+
INS_OPTS_SCALABLE_S); // ST1W {<Zt>.S }, <Pg>, [<Zn>.S{, #<imm>}]
7669+
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 0,
7670+
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7671+
theEmitter->emitIns_R_R_R_I(INS_sve_st1b, EA_SCALABLE, REG_V1, REG_P2, REG_V3, 31,
7672+
INS_OPTS_SCALABLE_D); // ST1B {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7673+
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 0,
7674+
INS_OPTS_SCALABLE_D); // ST1H {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7675+
theEmitter->emitIns_R_R_R_I(INS_sve_st1h, EA_SCALABLE, REG_V5, REG_P3, REG_V2, 62,
7676+
INS_OPTS_SCALABLE_D); // ST1H {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7677+
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 0,
7678+
INS_OPTS_SCALABLE_D); // ST1W {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7679+
theEmitter->emitIns_R_R_R_I(INS_sve_st1w, EA_SCALABLE, REG_V5, REG_P4, REG_V1, 124,
7680+
INS_OPTS_SCALABLE_D); // ST1W {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7681+
7682+
// IF_SVE_JL_3A
7683+
theEmitter->emitIns_R_R_R_I(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P7, REG_V4, 0,
7684+
INS_OPTS_SCALABLE_D); // ST1D {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7685+
theEmitter->emitIns_R_R_R_I(INS_sve_st1d, EA_SCALABLE, REG_V3, REG_P7, REG_V4, 248,
7686+
INS_OPTS_SCALABLE_D); // ST1D {<Zt>.D }, <Pg>, [<Zn>.D{, #<imm>}]
7687+
7688+
// IF_SVE_IC_3A
7689+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rd, EA_SCALABLE, REG_V1, REG_P2, REG_R3, 504,
7690+
INS_OPTS_SCALABLE_D); // LD1RD {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7691+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsw, EA_SCALABLE, REG_V4, REG_P5, REG_R6, 252,
7692+
INS_OPTS_SCALABLE_D); // LD1RSW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7693+
7694+
// IF_SVE_IC_3A_A
7695+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsh, EA_SCALABLE, REG_V0, REG_P1, REG_R2, 0,
7696+
INS_OPTS_SCALABLE_S); // LD1RSH {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7697+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rw, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 0,
7698+
INS_OPTS_SCALABLE_S); // LD1RW {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7699+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsh, EA_SCALABLE, REG_V0, REG_P1, REG_R2, 126,
7700+
INS_OPTS_SCALABLE_D); // LD1RSH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7701+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rw, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 252,
7702+
INS_OPTS_SCALABLE_D); // LD1RW {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7703+
7704+
// IF_SVE_IC_3A_B
7705+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rh, EA_SCALABLE, REG_V0, REG_P2, REG_R3, 0,
7706+
INS_OPTS_SCALABLE_H); // LD1RH {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7707+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsb, EA_SCALABLE, REG_V6, REG_P5, REG_R4, 0,
7708+
INS_OPTS_SCALABLE_H); // LD1RSB {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7709+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rh, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 126,
7710+
INS_OPTS_SCALABLE_S); // LD1RH {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7711+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsb, EA_SCALABLE, REG_V2, REG_P1, REG_R0, 63,
7712+
INS_OPTS_SCALABLE_S); // LD1RSB {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7713+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rh, EA_SCALABLE, REG_V3, REG_P2, REG_R1, 126,
7714+
INS_OPTS_SCALABLE_D); // LD1RH {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7715+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rsb, EA_SCALABLE, REG_V4, REG_P5, REG_R6, 63,
7716+
INS_OPTS_SCALABLE_D); // LD1RSB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7717+
7718+
// IF_SVE_IC_3A_C
7719+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V1, REG_P2, REG_R3, 0,
7720+
INS_OPTS_SCALABLE_B); // LD1RB {<Zt>.B }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7721+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V5, REG_P4, REG_R3, 63,
7722+
INS_OPTS_SCALABLE_H); // LD1RB {<Zt>.H }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7723+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V6, REG_P7, REG_R8, 0,
7724+
INS_OPTS_SCALABLE_S); // LD1RB {<Zt>.S }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
7725+
theEmitter->emitIns_R_R_R_I(INS_sve_ld1rb, EA_SCALABLE, REG_V1, REG_P0, REG_R9, 63,
7726+
INS_OPTS_SCALABLE_B); // LD1RB {<Zt>.D }, <Pg>/Z, [<Xn|SP>{, #<imm>}]
76017727
}
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#endif // defined(TARGET_ARM64) && defined(DEBUG)

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