Skip to content

Issues: IHP-GmbH/IHP-Open-PDK

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

45 Open 69 Closed
45 Open 69 Closed
Author
Filter by author
Loading
Label
Filter by label
Loading
Use alt + click/return to exclude labels
or ⇧ + click/return for logical OR
Projects
Filter by project
Loading
Milestones
Filter by milestone
Loading
Assignee
Filter by who’s assigned
Sort
Sort by
Newest Oldest Most commented Least commented Recently updated Least recently updated Best match
Most reactions
👍 👎 😄 🎉 😕 ❤️ 🚀 👀

Issues list

Transmission Line, Balun, Transformers are missing. question Further information is requested
#251 opened Nov 1, 2024 by rupokdas147
@KrzysztofHerman
1
Missing Cont in IO cells
#250 opened Oct 31, 2024 by dnltz
3
Can not run HBT example from Qucs-s using Xyce simulator enhancement New feature or request
#249 opened Oct 31, 2024 by rupokdas147
@KrzysztofHerman
11
Xyce sg13g2_moshv_stat.lib parameter question enhancement New feature or request
#248 opened Oct 30, 2024 by olisnr
@KrzysztofHerman
1
Need automatic generation of layout assembly (simple in-line, all with all) to run abutment checks for stdcells enhancement New feature or request
#247 opened Oct 30, 2024 by sergeiandreyev
4
NW.b violation when two ebufn_2 abutt themselves
#246 opened Oct 30, 2024 by smunaut
@KrzysztofHerman @b10346
6
Pad.kR rule vs openroad PAD
#245 opened Oct 30, 2024 by britovski
11
SRAM macros failing LVS bug Something isn't working
#239 opened Oct 28, 2024 by urish
@sergeiandreyev
8
decap cells should be marked "CORE SPACER" in lef enhancement New feature or request
#237 opened Oct 27, 2024 by gadfort
@KrzysztofHerman
Sealring Pcell dimenssion inconsistency
#235 opened Oct 24, 2024 by PhillipRambo
9
Missing requirements: psutil enhancement New feature or request
#226 opened Oct 18, 2024 by dnltz
7
Separate KLayout DRC script and XML wrapper enhancement New feature or request
#221 opened Oct 15, 2024 by mole99
2
[bug] Unexpected USE ANALOG bug Something isn't working
#218 opened Oct 10, 2024 by gudeh
@KrzysztofHerman @b10346
1
IO cells AnalogPad - enhancement enhancement New feature or request
#216 opened Oct 7, 2024 by KrzysztofHerman
@KrzysztofHerman
[bug] ifnone state-dependent path delay
#209 opened Sep 24, 2024 by likeamahoney
@b10346
5
[bug] LRM specify block delay path restrictions bug Something isn't working
#208 opened Sep 23, 2024 by likeamahoney
3
Simulation of MOSFET noise with ngspice question Further information is requested
#207 opened Sep 22, 2024 by 0y8w1x
9
how to use tolerances in LVS?
#203 opened Sep 17, 2024 by olisnr
5
DRC seem to miss error on GatPoly Gat.b or Gat.b1 bug Something isn't working
#201 opened Sep 16, 2024 by olisnr
25
missing NW.d1 in Figure 5.1 of "SG13G2 Layout Rules Rev. 0.3" documentation Improvements or additions to documentation
#199 opened Sep 12, 2024 by olisnr
1
top_lvl_pin
#192 opened Sep 3, 2024 by olisnr
10
PCells in KLayout bug Something isn't working
#188 opened Aug 28, 2024 by olisnr
@sergeiandreyev
9
PyPreprocessor & new python version invalid This doesn't seem right
#187 opened Aug 27, 2024 by KrzysztofHerman
@sergeiandreyev @KrzysztofHerman
1
large increase in area for ff compared to buf for upsize
#186 opened Aug 19, 2024 by maliberty
@b10346
2
Filler cells are missing in CDL/SPICE netlists bug Something isn't working
#184 opened Aug 13, 2024 by sergeiandreyev
@b10346
ProTip! Type g p on any issue or pull request to go back to the pull request listing page.