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PCells in KLayout #188
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I confirm that |
I cannot reproduce this, with the mentioned values I don't have |
on the first item, the device geometry is correct - we need to have one connection to Metal5 and another one to TopMetal1 |
when i use the latest commit (and also some versions before) KLayout (0.29.5 2024-7-31) schows errors at start up:
and after it i cant open the |
I guess we need to update our installation documentation.. |
thanks, now all is totally different :) now i get an M1.d error for the pmosHV at default settings. and for all pmosHV the normal LU.a error. i tryed to understand the latchup rules. but Figure 7.4: Latch-up protection rules SG13G2 Layout Rules Rev. 0.3 is not so clear for me. if i understand it right, thats only necessary in IO cells. the other thing i would like to know. how should i isolate sensitive circuits? whit a ring of |
updated documentation: |
this should be ok, as it is consistent with our commercial PDK on the latch-up rules - we're reviewing the questions.. |
i try to use nmosHV, pmosHV and cmim in KLayout from the last working SG13_dev version.
my BiG question is:
TopMetal1.drawing
. is this an error ?in DRC i get some errors:
2. pmosHV gives minimum errors DRC for pSD.i1 min 400nm, actual 340nm.
3. pmosHV has no GatPloy.pin but nmosHV has. is GatPloy.pin needed for production?
4. if i use an w=2u l=1u pmosHV i get also NW.d1 and LU.a errors
will this be fixed, or is the idea to draw pSD and ThickGateOxyde in the end from hand, when the FETs are placed?
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