top_lvl_pin

[olisnr]

how are top-level-pins made in KLayout?
there are MetalN.pin, TopMetalN.pin and GatePoly.pin layers. but there are also the *.text layers.
is a top_lvl_pin for the LVS-script a combination of *.pin and *.text, or something different?

[FaragElsayed2]

@olisnr

Text layer only

IHP-Open-PDK/ihp-sg13g2/libs.tech/klayout/tech/lvs/rule_decks/general_connections.lvs

Line 55 in 5a42d03

# Attaching labels

[olisnr]

@FaragElsayed2

thanks. is this also working for GatPoly?

[atorkmabrains]

@olisnr No, only metals.

Is that a request for change?

@sergeiandreyev Do you want us to change that and allow adding text on poly layer?

[olisnr]

@FaragElsayed2 i think for the MOSFETs it would be necessary. otherwise its not possible to route direct via GatPoly...

[sergeiandreyev]

@atorkmabrains, I'm not sure if there was such request before
let me check on this internally
How it's done in commercial PDK?
Frank will be next week I hope, so we can discuss from both sides

[atorkmabrains]

@olisnr Are you using automated routing for MOSFETs?

It's unconventional in custom design to need text on poly. Usually, you need pins for the ports of your cells/blocks. There might be some use case of supporting this and it's not a big change for us.

@sergeiandreyev I'm not sure how it was implemented in commercial PDK, but we will check and get back to you.

[olisnr]

@FaragElsayed2 at the moment i make manual routed analog.
if one does an OTA or some bias-circuit, then it could be interesting to connect direct to the gates, instead to make some vias to a metal-level thats not really needed on the wrong side of the big MOSFET.

[FaragElsayed2]

@atorkmabrains @sergeiandreyev @olisnr

BTW, there is no text layer for poly in the PDK.

[atorkmabrains]

@olisnr Just to confirm, you mean routing using Poly? Poly routing is not recommended. Poly has high resistivity and noisy routing layer. Just from the electronics point of view.

But as you say, we should cater for any kind of designer. Anyhow, we will check how it's done in the Commercial PDK and get back to you.

[olisnr]

i only want to rout over GatPoly.drawing if two gates are very near. but it would interessting also when i want to route over metal from a big FET. because, if i have a pin on GatPoly.drawing i can place the Cont.drawing via at the best place, instead of being forced to use predefined vias...

i would like to know, if You think this kind of GatPoly.drawing-routing is a problem:

OTAtest_small.gds.zip