Feature/add documentation #9
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| To develop on Xilinx FPGAs, there are a couple of workflows: | ||
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| 1. Legacy HLS -> Vivado workflow |
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Maybe providing a section that goes through the useful resources for following the legacy HLS workflow might be handy, in a separate md file as an appendix.
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| To develop on Xilinx FPGAs, there are a couple of workflows: | ||
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| 1. Legacy HLS -> Vivado workflow | ||
| 2. Vitis Kernel workflow (newest) |
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Maybe a comparison matrix can be made as a resource which can be useful if this information has to be consulted on a regular basis.
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| auto dma = platform->GetDataMover(kDmaAddress); | ||
| ``` | ||
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| where `kDmaAddress` is the address of the DMA instance we want to control. This is given by the design. |
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Define what a design means in this context.
| > The IP Cores must have an AXI4-Lite port as a control port | ||
| 5) Get buffers to exchange data. These buffers are usually dual memory: they are mapped into host and device regions (physically contiguous). |
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make examples of how these memory addresses look like, maybe making a diagram for this in the future can help illustrate this.
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docs/GettingStarted.md
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| out_mem->Sync(SyncType::DeviceToHost); | ||
| ``` | ||
| that takes any of the following values: |
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any can be interpreted as a list of values, clarify that only ONE value is passed to the method but it is ONE from the list provided.
This adds the documentation files required for deployment
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