Update readme

Now it includes links and citation

Author: lleoncr

README.md

@@ -60,8 +60,8 @@ With CYNQ:
 using namespace cynq;
 
 // Configure the FPGA
-auto kArquitecture = HardwareArchitecture::UltraScale;
-auto platform = IHardware::Create(kArquitecture, "design.bit", "default.xclbin");
+auto kArch = HardwareArchitecture::UltraScale;
+auto platform = IHardware::Create(kArch, "design.bit", "default.xclbin");
 
 // Extract the accelerator (IP Core) and DMA
 // Addresses are given by the design
@@ -89,3 +89,22 @@ outbuf->Sync(SyncType::DeviceToHost);
 So far, we have tested CYNQ on:
 
 1. Xilinx KV26-based with Ubuntu 2022.04
+
+## Links & References:
+
+* Docs: https://ecaslab.github.io/cynq
+* Github: https://github.com/ECASLab/cynq
+
+Cite Us:
+
+```
+@misc{blabla,
+  author = {{León-vega, Luis G.
+              AND Ávila-Torres, Diego
+              AND Castro-Godínez, Jorge
+            }},
+  title = {{CYNQ (v0.1)}},
+  year  = {2023},
+  url   = {https://github.com/ECASLab/cynq},
+} 
+```

docs/Doxyfile.in

@@ -291,7 +291,7 @@ OPTIMIZE_OUTPUT_VHDL   = NO
 # Note that for custom extensions you also need to set FILE_PATTERNS otherwise
 # the files are not read by doxygen.
 
-EXTENSION_MAPPING      =
+EXTENSION_MAPPING      = 
 
 # If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
 # according to the Markdown format, which allows for more readable

docs/html/index.html

@@ -116,13 +116,19 @@ <h2>Index</h2>
 <h2>How does CYNQ look like?</h2>
 <p>CYNQ is pretty similar to PYNQ, let's have a look.</p>
 <p>PYNQ:</p>
-<div class="fragment"><div class="line">from pynq <span class="keyword">import</span> allocate, Overlay</div><div class="line"></div><div class="line"><span class="comment"># Configure the FPGA</span></div><div class="line">design = Overlay(<span class="stringliteral">&quot;design.bit&quot;</span>)</div><div class="line"></div><div class="line"><span class="comment"># Extract the accelerator (IP Core) and DMA</span></div><div class="line">dma = design.axi_dma_0</div><div class="line">accel = design.multiplication_accel_0</div><div class="line"></div><div class="line"><span class="comment"># Allocate buffers</span></div><div class="line">inbuf = allocate(shape=(input_elements,), dtype=np.uint16)</div><div class="line">outbuf = allocate(shape=(output_elements,), dtype=np.uint16)</div><div class="line"></div><div class="line"><span class="comment"># Run</span></div><div class="line">dma.sendchannel.transfer(inbuf)</div><div class="line">accel.write(accel.register_map.CTRL.address, 0x81)</div><div class="line">dma.recvchannel.transfer(outbuf)</div><div class="line">dma.recvchannel.wait()</div><div class="line"></div><div class="line"><span class="comment"># Dispose the buffers</span></div><div class="line">del input_hw</div><div class="line">del output_hw</div></div><!-- fragment --><p>With CYNQ:</p>
-<div class="fragment"><div class="line"><span class="preprocessor">#include &lt;cynq/cynq.hpp&gt;</span></div><div class="line"></div><div class="line"><span class="keyword">using namespace </span><a class="code" href="namespacecynq.html">cynq</a>;</div><div class="line"></div><div class="line"><span class="comment">// Configure the FPGA</span></div><div class="line"><span class="keyword">auto</span> kArquitecture = HardwareArchitecture::UltraScale;</div><div class="line"><span class="keyword">auto</span> platform = <a class="code" href="classcynq_1_1IHardware.html#ab3cc41fbed5a6da306d8ae51153a3065">IHardware::Create</a>(kArquitecture, <span class="stringliteral">&quot;design.bit&quot;</span>, <span class="stringliteral">&quot;default.xclbin&quot;</span>);</div><div class="line"></div><div class="line"><span class="comment">// Extract the accelerator (IP Core) and DMA</span></div><div class="line"><span class="comment">// Addresses are given by the design</span></div><div class="line"><span class="keyword">auto</span> accel = platform-&gt;GetAccelerator(0xa000000);</div><div class="line"><span class="keyword">auto</span> dma = platform-&gt;GetDataMover(0xa0010000);</div><div class="line"></div><div class="line"><span class="comment">// Allocate buffers and get the pointers</span></div><div class="line"><span class="keyword">auto</span> inbuf = mover-&gt;GetBuffer(input_size);</div><div class="line"><span class="keyword">auto</span> outbuf = mover-&gt;GetBuffer(output_size);</div><div class="line">uint16_t* input_ptr = inbuf-&gt;HostAddress&lt;uint16_t&gt;().<span class="keyword">get</span>();</div><div class="line">uint16_t* output_ptr = outbuf-&gt;HostAddress&lt;uint16_t&gt;().<span class="keyword">get</span>();</div><div class="line"></div><div class="line"><span class="comment">// Run</span></div><div class="line">accel-&gt;Start(StartMode::Continuous);</div><div class="line">inbuf-&gt;Sync(SyncType::HostToDevice);</div><div class="line">mover-&gt;Upload(in_mem, infbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">mover-&gt;Download(out_mem, outbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">outbuf-&gt;Sync(SyncType::DeviceToHost);</div><div class="line"></div><div class="line"><span class="comment">// Dispose? We use RAII</span></div></div><!-- fragment --><h2>Currently tested</h2>
+<div class="fragment"><div class="line">from pynq import allocate, Overlay</div><div class="line"></div><div class="line"># Configure the FPGA</div><div class="line">design = Overlay(&quot;design.bit&quot;)</div><div class="line"></div><div class="line"># Extract the accelerator (IP Core) and DMA</div><div class="line">dma = design.axi_dma_0</div><div class="line">accel = design.multiplication_accel_0</div><div class="line"></div><div class="line"># Allocate buffers</div><div class="line">inbuf = allocate(shape=(input_elements,), dtype=np.uint16)</div><div class="line">outbuf = allocate(shape=(output_elements,), dtype=np.uint16)</div><div class="line"></div><div class="line"># Run</div><div class="line">dma.sendchannel.transfer(inbuf)</div><div class="line">accel.write(accel.register_map.CTRL.address, 0x81)</div><div class="line">dma.recvchannel.transfer(outbuf)</div><div class="line">dma.recvchannel.wait()</div><div class="line"></div><div class="line"># Dispose the buffers</div><div class="line">del input_hw</div><div class="line">del output_hw</div></div><!-- fragment --><p>With CYNQ:</p>
+<div class="fragment"><div class="line">{c++}</div><div class="line">#include &lt;cynq/cynq.hpp&gt;</div><div class="line"></div><div class="line">using namespace cynq;</div><div class="line"></div><div class="line">// Configure the FPGA</div><div class="line">auto kArch = HardwareArchitecture::UltraScale;</div><div class="line">auto platform = IHardware::Create(kArch, &quot;design.bit&quot;, &quot;default.xclbin&quot;);</div><div class="line"></div><div class="line">// Extract the accelerator (IP Core) and DMA</div><div class="line">// Addresses are given by the design</div><div class="line">auto accel = platform-&gt;GetAccelerator(0xa000000);</div><div class="line">auto dma = platform-&gt;GetDataMover(0xa0010000);</div><div class="line"></div><div class="line">// Allocate buffers and get the pointers</div><div class="line">auto inbuf = mover-&gt;GetBuffer(input_size);</div><div class="line">auto outbuf = mover-&gt;GetBuffer(output_size);</div><div class="line">uint16_t* input_ptr = inbuf-&gt;HostAddress&lt;uint16_t&gt;().get();</div><div class="line">uint16_t* output_ptr = outbuf-&gt;HostAddress&lt;uint16_t&gt;().get();</div><div class="line"></div><div class="line">// Run</div><div class="line">accel-&gt;Start(StartMode::Continuous);</div><div class="line">inbuf-&gt;Sync(SyncType::HostToDevice);</div><div class="line">mover-&gt;Upload(in_mem, infbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">mover-&gt;Download(out_mem, outbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">outbuf-&gt;Sync(SyncType::DeviceToHost);</div><div class="line"></div><div class="line">// Dispose? We use RAII</div></div><!-- fragment --><h2>Currently tested</h2>
 <p>So far, we have tested CYNQ on:</p>
 <ol type="1">
-<li>Xilinx KV26-based with Ubuntu 2022.04 </li>
+<li>Xilinx KV26-based with Ubuntu 2022.04</li>
 </ol>
-</div></div><!-- contents -->
+<h2>Links &amp; References:</h2>
+<ul>
+<li>Docs: <a href="https://ecaslab.github.io/cynq">https://ecaslab.github.io/cynq</a></li>
+<li>Github: <a href="https://github.com/ECASLab/cynq">https://github.com/ECASLab/cynq</a></li>
+</ul>
+<p>Cite Us:</p>
+<div class="fragment"><div class="line">@misc{blabla,</div><div class="line">  author = {{León-vega, Luis G.</div><div class="line">              AND Ávila-Torres, Diego</div><div class="line">              AND Castro-Godínez, Jorge</div><div class="line">            }},</div><div class="line">  title = {{CYNQ (v0.1)}},</div><div class="line">  year  = {2023},</div><div class="line">  url   = {https://github.com/ECASLab/cynq},</div><div class="line">} </div></div><!-- fragment --> </div></div><!-- contents -->
 </div><!-- doc-content -->
 <!-- start footer part -->
 <div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->

docs/html/md__media_lleon95_data_Personal_cynq_docs_GettingStarted.html

@@ -138,8 +138,8 @@
 <p>To synchronise the buffers, it is possible to use <code>Sync()</code> method:</p>
 <div class="fragment"><div class="line">{c++}</div><div class="line">in_mem-&gt;Sync(SyncType::HostToDevice);</div><div class="line">out_mem-&gt;Sync(SyncType::DeviceToHost);</div></div><!-- fragment --><p>that takes any of the following values:</p>
 <ul>
-<li>cynq::SyncType::DeviceToHost: device to host synchronisation</li>
-<li>cynq::SyncType::HostToDevice: host to device synchronisation</li>
+<li><code>cynq::SyncType::DeviceToHost</code>: device to host synchronisation</li>
+<li><code>cynq::SyncType::HostToDevice</code>: host to device synchronisation</li>
 </ul>
 <p>Once the memory is synchronised, the data mover is used to upload the data to the AXI4-Stream or download from it.</p>
 <div class="fragment"><div class="line">{c++}</div><div class="line">// Upload: requires the buffer to be sync in HostToDevice</div><div class="line">dma-&gt;Upload(in_mem, in_mem-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">// Download: after its completion, the buffer must be sync DeviceToHost</div><div class="line">dma-&gt;Download(out_mem, out_mem-&gt;Size(), 0, ExecutionType::Sync);</div></div><!-- fragment --><p>Both methods takes: <code>(memory, size, offset, execution_type)</code>, where <code>size</code> is the amount of data to transfer in bytes, <code>offset</code> moves the starting point of the data and <code>execution_type</code> is the type of execution:</p>