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Update readme
Now it includes links and citation
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‎README.md‎

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@@ -17,6 +17,7 @@ CYNQ is a C++ framework to implement FPGA-based accelerated applications with th
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## Index
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* [Foundations](docs/Foundations.md)
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* [Class Diagram](docs/ClassDiagram.md)
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* [Installation](docs/Installation.md)
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* [Getting Started](docs/GettingStarted.md)
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* [About](docs/About.md)
@@ -60,8 +61,8 @@ With CYNQ:
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using namespace cynq;
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// Configure the FPGA
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auto kArquitecture = HardwareArchitecture::UltraScale;
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auto platform = IHardware::Create(kArquitecture, "design.bit", "default.xclbin");
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auto kArch = HardwareArchitecture::UltraScale;
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auto platform = IHardware::Create(kArch, "design.bit", "default.xclbin");
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// Extract the accelerator (IP Core) and DMA
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// Addresses are given by the design
@@ -89,3 +90,22 @@ outbuf->Sync(SyncType::DeviceToHost);
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So far, we have tested CYNQ on:
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1. Xilinx KV26-based with Ubuntu 2022.04
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## Links & References:
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* Docs: https://ecaslab.github.io/cynq
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* Github: https://github.com/ECASLab/cynq
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Cite Us:
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```
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@misc{blabla,
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author = {{León-vega, Luis G.
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AND Ávila-Torres, Diego
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AND Castro-Godínez, Jorge
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}},
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title = {{CYNQ (v0.1)}},
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year = {2023},
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url = {https://github.com/ECASLab/cynq},
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}
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```

‎docs/ClassDiagram.md‎

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# Class Diagram
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@startuml
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interface IHardware {
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+{abstract} Reset() -> Status
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+{abstract} GetDataMover(address) -> IDataMover *
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+{abstract} GetAccelerator(address) -> IAccelerator *
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+{static} Create(hw: HardwareArchitecture, bitstream: string, xclbin: string) -> IHardware*
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}
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interface IMemory {
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{abstract} #GetHostAddress() -> uint8_t *
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{abstract} #GetDeviceAddress() -> uint8_t *
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+HostAddress<T>() -> T *
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+DeviceAddress<T>() -> T *
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{abstract} Sync(type: SyncType) -> Status
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{abstract} Size() -> size_t
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+{static} Create(impl: IMemoryType, size, hostptr, devptr) -> IMemory*
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}
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enum IMemoryType {
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XRT
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CMA
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ALIGNED
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}
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IMemoryType ..o IMemory
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interface IAccelerator {
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{abstract} Start(mode: StartMode) -> Status
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{abstract} Stop() -> Status
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{abstract} #WriteRegister(address, data: uint8_t*, size: size_t) -> Status
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{abstract} #ReadRegister(address, data: uint8_t*, size: size_t) -> Status
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+Write<T>(address, data: T*, elems: size_t) -> Status
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+Read<T>(address, data: T*, elems: size_t) -> Status
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{abstract} GetStatus() -> DeviceStatus
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+{static} Create(impl: IAcceleratorType, addr: uint64) -> IAccelerator*
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}
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enum IAcceleratorType {
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XRT
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MMIO
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CHAR
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}
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IAcceleratorType ..o IAccelerator
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interface IDataMover {
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{abstract} GetBuffer(size: size_t, type: MemoryType) -> IMemory *
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{abstract} Upload(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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{abstract} Download(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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{abstract} Sync() -> Status
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{abstract} GetStatus() -> DeviceStatus
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+{static} Create(impl: IDataMoverType, addr: uint64) -> IDataMover*
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}
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enum IDataMoverType {
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XRT
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DMA
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XDMA
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}
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IDataMoverType ..o IDataMover
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enum HardwareArchitecture {
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UltraScale
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Zynq
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XDMA
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Alveo
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}
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HardwareArchitecture ..o IHardware
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enum SyncType {
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HostToDevice,
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DeviceToHost,
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}
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enum StartMode {
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Once,
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Continuous
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}
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enum MemoryType {
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Dual,
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Cacheable,
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Host,
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Device
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}
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enum DeviceStatus {
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Unknown,
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Done,
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Idle,
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Running,
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Error
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}
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enum ExecutionType {
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Sync,
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Async
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}
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class UltraScale {
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+Reset() -> Status
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+GetDataMover(address) -> XRTDataMover *
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+GetAccelerator(address) -> AmdAccelerator *
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+UltraScale(hw, bitsteam, xclbin)
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}
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class XRTMemory {
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#GetHostAddress() -> uint8_t *
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#GetDeviceAddress() -> uint8_t *
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Sync(type: SyncType) -> Status
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Size() -> size_t
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+XRTMemory(hostptr, devptr)
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}
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class XRTAccelerator {
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Start(mode: StartMode) -> Status
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Stop() -> Status
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GetStatus() -> DeviceStatus
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#WriteRegister(address, data: uint8_t*, size: size_t) -> Status
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#ReadRegister(address, data: uint8_t*, size: size_t) -> Status
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+AmdAccelerator(addr: uint64)
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}
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class XRTDataMover {
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GetBuffer(size: size_t, type: MemoryType) -> XRTMemory *
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Upload(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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Download(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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Sync() -> Status
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GetStatus() -> DeviceStatus
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XRTDataMover(addr)
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}
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UltraScale ..> IHardware
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XRTMemory ..> IMemory
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XRTAccelerator ..> IAccelerator
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XRTDataMover ..> IDataMover
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@enduml

‎docs/Doxyfile.in‎

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@@ -291,7 +291,7 @@ OPTIMIZE_OUTPUT_VHDL = NO
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# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
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# the files are not read by doxygen.
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EXTENSION_MAPPING =
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EXTENSION_MAPPING =
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# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
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# according to the Markdown format, which allows for more readable

‎docs/Foundations.md‎

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@@ -53,144 +53,4 @@ As it is possible to see, there is an equivalence at the functional level.
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Going deeper, how CYNQ is currently mounted for the Xilinx Kria, it uses XRT for the buffers, MMIO for accelerators and data mover and FPGA manager for the hardware configuration.
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A rough estimation of the class diagram is the following:
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@startuml
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interface IHardware {
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+{abstract} Reset() -> Status
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+{abstract} GetDataMover(address) -> IDataMover *
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+{abstract} GetAccelerator(address) -> IAccelerator *
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+{static} Create(hw: HardwareArchitecture, bitstream: string, xclbin: string) -> IHardware*
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}
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interface IMemory {
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{abstract} #GetHostAddress() -> uint8_t *
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{abstract} #GetDeviceAddress() -> uint8_t *
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+HostAddress<T>() -> T *
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+DeviceAddress<T>() -> T *
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{abstract} Sync(type: SyncType) -> Status
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{abstract} Size() -> size_t
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+{static} Create(impl: IMemoryType, size, hostptr, devptr) -> IMemory*
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}
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enum IMemoryType {
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XRT
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CMA
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ALIGNED
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}
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IMemoryType ..o IMemory
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interface IAccelerator {
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{abstract} Start(mode: StartMode) -> Status
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{abstract} Stop() -> Status
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{abstract} #WriteRegister(address, data: uint8_t*, size: size_t) -> Status
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{abstract} #ReadRegister(address, data: uint8_t*, size: size_t) -> Status
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+Write<T>(address, data: T*, elems: size_t) -> Status
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+Read<T>(address, data: T*, elems: size_t) -> Status
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{abstract} GetStatus() -> DeviceStatus
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+{static} Create(impl: IAcceleratorType, addr: uint64) -> IAccelerator*
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}
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enum IAcceleratorType {
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XRT
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MMIO
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CHAR
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}
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IAcceleratorType ..o IAccelerator
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interface IDataMover {
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{abstract} GetBuffer(size: size_t, type: MemoryType) -> IMemory *
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{abstract} Upload(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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{abstract} Download(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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{abstract} Sync() -> Status
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{abstract} GetStatus() -> DeviceStatus
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+{static} Create(impl: IDataMoverType, addr: uint64) -> IDataMover*
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}
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enum IDataMoverType {
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XRT
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DMA
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XDMA
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}
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IDataMoverType ..o IDataMover
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119-
enum HardwareArchitecture {
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UltraScale
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Zynq
122-
XDMA
123-
Alveo
124-
}
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HardwareArchitecture ..o IHardware
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128-
enum SyncType {
129-
HostToDevice,
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DeviceToHost,
131-
}
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133-
enum StartMode {
134-
Once,
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Continuous
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}
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enum MemoryType {
139-
Dual,
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Cacheable,
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Host,
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Device
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}
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enum DeviceStatus {
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Unknown,
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Done,
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Idle,
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Running,
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Error
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}
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enum ExecutionType {
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Sync,
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Async
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}
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159-
class UltraScale {
160-
+Reset() -> Status
161-
+GetDataMover(address) -> XRTDataMover *
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+GetAccelerator(address) -> AmdAccelerator *
163-
+UltraScale(hw, bitsteam, xclbin)
164-
}
165-
166-
class XRTMemory {
167-
#GetHostAddress() -> uint8_t *
168-
#GetDeviceAddress() -> uint8_t *
169-
Sync(type: SyncType) -> Status
170-
Size() -> size_t
171-
+XRTMemory(hostptr, devptr)
172-
}
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174-
class XRTAccelerator {
175-
Start(mode: StartMode) -> Status
176-
Stop() -> Status
177-
GetStatus() -> DeviceStatus
178-
#WriteRegister(address, data: uint8_t*, size: size_t) -> Status
179-
#ReadRegister(address, data: uint8_t*, size: size_t) -> Status
180-
+AmdAccelerator(addr: uint64)
181-
}
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183-
class XRTDataMover {
184-
GetBuffer(size: size_t, type: MemoryType) -> XRTMemory *
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Upload(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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Download(mem: IMemory, size: size_t, exetype: ExecutionType) -> Status
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Sync() -> Status
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GetStatus() -> DeviceStatus
189-
XRTDataMover(addr)
190-
}
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192-
UltraScale ..> IHardware
193-
XRTMemory ..> IMemory
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XRTAccelerator ..> IAccelerator
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XRTDataMover ..> IDataMover
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@enduml
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See more in [Class Diagram](ClassDiagram.md)

‎docs/html/index.html‎

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</ol>
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<h2>Index</h2>
110110
<ul>
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<li>Foundations</li>
111+
<li>Foundations<ul>
112+
<li>Class Diagram</li>
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</ul>
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</li>
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<li>Installation</li>
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<li>Getting Started</li>
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<li>About</li>
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</ul>
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<h2>How does CYNQ look like?</h2>
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<p>CYNQ is pretty similar to PYNQ, let's have a look.</p>
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<p>PYNQ:</p>
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<div class="fragment"><div class="line">from pynq <span class="keyword">import</span> allocate, Overlay</div><div class="line"></div><div class="line"><span class="comment"># Configure the FPGA</span></div><div class="line">design = Overlay(<span class="stringliteral">&quot;design.bit&quot;</span>)</div><div class="line"></div><div class="line"><span class="comment"># Extract the accelerator (IP Core) and DMA</span></div><div class="line">dma = design.axi_dma_0</div><div class="line">accel = design.multiplication_accel_0</div><div class="line"></div><div class="line"><span class="comment"># Allocate buffers</span></div><div class="line">inbuf = allocate(shape=(input_elements,), dtype=np.uint16)</div><div class="line">outbuf = allocate(shape=(output_elements,), dtype=np.uint16)</div><div class="line"></div><div class="line"><span class="comment"># Run</span></div><div class="line">dma.sendchannel.transfer(inbuf)</div><div class="line">accel.write(accel.register_map.CTRL.address, 0x81)</div><div class="line">dma.recvchannel.transfer(outbuf)</div><div class="line">dma.recvchannel.wait()</div><div class="line"></div><div class="line"><span class="comment"># Dispose the buffers</span></div><div class="line">del input_hw</div><div class="line">del output_hw</div></div><!-- fragment --><p>With CYNQ:</p>
120-
<div class="fragment"><div class="line"><span class="preprocessor">#include &lt;cynq/cynq.hpp&gt;</span></div><div class="line"></div><div class="line"><span class="keyword">using namespace </span><a class="code" href="namespacecynq.html">cynq</a>;</div><div class="line"></div><div class="line"><span class="comment">// Configure the FPGA</span></div><div class="line"><span class="keyword">auto</span> kArquitecture = HardwareArchitecture::UltraScale;</div><div class="line"><span class="keyword">auto</span> platform = <a class="code" href="classcynq_1_1IHardware.html#ab3cc41fbed5a6da306d8ae51153a3065">IHardware::Create</a>(kArquitecture, <span class="stringliteral">&quot;design.bit&quot;</span>, <span class="stringliteral">&quot;default.xclbin&quot;</span>);</div><div class="line"></div><div class="line"><span class="comment">// Extract the accelerator (IP Core) and DMA</span></div><div class="line"><span class="comment">// Addresses are given by the design</span></div><div class="line"><span class="keyword">auto</span> accel = platform-&gt;GetAccelerator(0xa000000);</div><div class="line"><span class="keyword">auto</span> dma = platform-&gt;GetDataMover(0xa0010000);</div><div class="line"></div><div class="line"><span class="comment">// Allocate buffers and get the pointers</span></div><div class="line"><span class="keyword">auto</span> inbuf = mover-&gt;GetBuffer(input_size);</div><div class="line"><span class="keyword">auto</span> outbuf = mover-&gt;GetBuffer(output_size);</div><div class="line">uint16_t* input_ptr = inbuf-&gt;HostAddress&lt;uint16_t&gt;().<span class="keyword">get</span>();</div><div class="line">uint16_t* output_ptr = outbuf-&gt;HostAddress&lt;uint16_t&gt;().<span class="keyword">get</span>();</div><div class="line"></div><div class="line"><span class="comment">// Run</span></div><div class="line">accel-&gt;Start(StartMode::Continuous);</div><div class="line">inbuf-&gt;Sync(SyncType::HostToDevice);</div><div class="line">mover-&gt;Upload(in_mem, infbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">mover-&gt;Download(out_mem, outbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">outbuf-&gt;Sync(SyncType::DeviceToHost);</div><div class="line"></div><div class="line"><span class="comment">// Dispose? We use RAII</span></div></div><!-- fragment --><h2>Currently tested</h2>
122+
<div class="fragment"><div class="line">from pynq import allocate, Overlay</div><div class="line"></div><div class="line"># Configure the FPGA</div><div class="line">design = Overlay(&quot;design.bit&quot;)</div><div class="line"></div><div class="line"># Extract the accelerator (IP Core) and DMA</div><div class="line">dma = design.axi_dma_0</div><div class="line">accel = design.multiplication_accel_0</div><div class="line"></div><div class="line"># Allocate buffers</div><div class="line">inbuf = allocate(shape=(input_elements,), dtype=np.uint16)</div><div class="line">outbuf = allocate(shape=(output_elements,), dtype=np.uint16)</div><div class="line"></div><div class="line"># Run</div><div class="line">dma.sendchannel.transfer(inbuf)</div><div class="line">accel.write(accel.register_map.CTRL.address, 0x81)</div><div class="line">dma.recvchannel.transfer(outbuf)</div><div class="line">dma.recvchannel.wait()</div><div class="line"></div><div class="line"># Dispose the buffers</div><div class="line">del input_hw</div><div class="line">del output_hw</div></div><!-- fragment --><p>With CYNQ:</p>
123+
<div class="fragment"><div class="line">{c++}</div><div class="line">#include &lt;cynq/cynq.hpp&gt;</div><div class="line"></div><div class="line">using namespace cynq;</div><div class="line"></div><div class="line">// Configure the FPGA</div><div class="line">auto kArch = HardwareArchitecture::UltraScale;</div><div class="line">auto platform = IHardware::Create(kArch, &quot;design.bit&quot;, &quot;default.xclbin&quot;);</div><div class="line"></div><div class="line">// Extract the accelerator (IP Core) and DMA</div><div class="line">// Addresses are given by the design</div><div class="line">auto accel = platform-&gt;GetAccelerator(0xa000000);</div><div class="line">auto dma = platform-&gt;GetDataMover(0xa0010000);</div><div class="line"></div><div class="line">// Allocate buffers and get the pointers</div><div class="line">auto inbuf = mover-&gt;GetBuffer(input_size);</div><div class="line">auto outbuf = mover-&gt;GetBuffer(output_size);</div><div class="line">uint16_t* input_ptr = inbuf-&gt;HostAddress&lt;uint16_t&gt;().get();</div><div class="line">uint16_t* output_ptr = outbuf-&gt;HostAddress&lt;uint16_t&gt;().get();</div><div class="line"></div><div class="line">// Run</div><div class="line">accel-&gt;Start(StartMode::Continuous);</div><div class="line">inbuf-&gt;Sync(SyncType::HostToDevice);</div><div class="line">mover-&gt;Upload(in_mem, infbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">mover-&gt;Download(out_mem, outbuf-&gt;Size(), 0, ExecutionType::Sync);</div><div class="line">outbuf-&gt;Sync(SyncType::DeviceToHost);</div><div class="line"></div><div class="line">// Dispose? We use RAII</div></div><!-- fragment --><h2>Currently tested</h2>
121124
<p>So far, we have tested CYNQ on:</p>
122125
<ol type="1">
123-
<li>Xilinx KV26-based with Ubuntu 2022.04 </li>
126+
<li>Xilinx KV26-based with Ubuntu 2022.04</li>
124127
</ol>
125-
</div></div><!-- contents -->
128+
<h2>Links &amp; References:</h2>
129+
<ul>
130+
<li>Docs: <a href="https://ecaslab.github.io/cynq">https://ecaslab.github.io/cynq</a></li>
131+
<li>Github: <a href="https://github.com/ECASLab/cynq">https://github.com/ECASLab/cynq</a></li>
132+
</ul>
133+
<p>Cite Us:</p>
134+
<div class="fragment"><div class="line">@misc{blabla,</div><div class="line"> author = {{León-vega, Luis G.</div><div class="line"> AND Ávila-Torres, Diego</div><div class="line"> AND Castro-Godínez, Jorge</div><div class="line"> }},</div><div class="line"> title = {{CYNQ (v0.1)}},</div><div class="line"> year = {2023},</div><div class="line"> url = {https://github.com/ECASLab/cynq},</div><div class="line">} </div></div><!-- fragment --> </div></div><!-- contents -->
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</div><!-- doc-content -->
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<!-- start footer part -->
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<div id="nav-path" class="navpath"><!-- id is needed for treeview function! -->

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