Update docs to fix typos

This fixes some typos on docs

Author: lleoncr

docs/About.md

@@ -9,13 +9,13 @@ CYNQ is an alternative framework to code applications for Xilinx FPGAs with the
 
 This project is completely Open Source thanks to:
 
-* Ministero dell'Università e della Ricerca
+* Ministero dell'Università e della Ricerca: Fellowship
 * University of Trieste
 * Costa Rica Institute of Technology
-* eXact Lab
-* RidgeRun LLC
+* eXact Lab: Partial fellowship
+* RidgeRun LLC: Tooling and FPGA boards
 
-Our goal is to keep it Open Source, accesible and powerful. Collaboration and improvements are very welcome.
+Our goal is to keep it Open Source, accessible and powerful. Collaboration and improvements are very welcome.
 
 The current maintainers are:
 

docs/Foundations.md

@@ -7,9 +7,9 @@ To develop on Xilinx FPGAs, there are a couple of workflows:
 1. Legacy HLS -> Vivado workflow
 2. Vitis Kernel workflow (newest)
 
-The first workflow is general and works in most of the use cases, independently if the FPGA is intended for Cloud, Edge or instrumental use (like Spartan and Artix). The key artifact is a bitstream (.bit) used for configuring the FPGA, requiring only Vitis/Vivado HLS and Vivado Design Suite.
+The first workflow is general and works in most use cases, independently of the FPGA is intended for Cloud, Edge or instrumental use (like Spartan and Artix). The key artifact is a bitstream (.bit) used for configuring the FPGA, requiring only Vitis/Vivado HLS and Vivado Design Suite.
 
-The second workflow is most specific for acceleration. It is used in modern MPSoCs and cloud-grade FPGAs. The key artifact is a binary (.xclbin) that is produced by a long chain of: Vitis HLS, Vivado Design Suite, Petalinux and Vitis. As you may notice, it's more tedious and require more tooling, consuming more storage in the development machine.
+The second workflow is most specific for acceleration. It is used in modern MPSoCs and cloud-grade FPGAs. The key artifact is a binary (.xclbin) that is produced by a long chain of: Vitis HLS, Vivado Design Suite, Petalinux and Vitis. As you may notice, it's more tedious and requires more tooling, consuming more storage in the development machine.
 
 PYNQ, particularly, has been characterised by its simplicity, only requiring the bitstream to work. It has also proved to be effective in a wide variety of boards, namely ZYNQ MPSoC and Alveo cards. In contrast, the new workflow requires more expertise in the tooling but produces better applications in terms of performance. However, the former one sacrifices a lot of the simplicity.
 
@@ -29,7 +29,7 @@ Within our plans, we want to:
 * Complete the support for XRT interoperability.
 * Provide a library with math kernels.
 
-This first release is a huge advance towards simplicity and we expect that many users look at CYNQ as the chance that they were waiting for to get started into the FPGA world, as seen in PYNQ.
+This first release is a huge advance towards simplicity and we expect that many users look at CYNQ as the chance that they were waiting for to get started in the FPGA world, as seen in PYNQ.
 
 ## How does CYNQ work?
 

docs/html/md__media_lleon95_data_Personal_cynq_docs_About.html

@@ -104,13 +104,13 @@
 </ul>
 <p>This project is completely Open Source thanks to:</p>
 <ul>
-<li>Ministero dell'Università e della Ricerca</li>
+<li>Ministero dell'Università e della Ricerca: Fellowship</li>
 <li>University of Trieste</li>
 <li>Costa Rica Institute of Technology</li>
-<li>eXact Lab</li>
-<li>RidgeRun LLC</li>
+<li>eXact Lab: Partial fellowship</li>
+<li>RidgeRun LLC: Tooling and FPGA boards</li>
 </ul>
-<p>Our goal is to keep it Open Source, accesible and powerful. Collaboration and improvements are very welcome.</p>
+<p>Our goal is to keep it Open Source, accessible and powerful. Collaboration and improvements are very welcome.</p>
 <p>The current maintainers are:</p>
 <ul>
 <li>Luis G. Leon Vega <a href="#" onclick="location.href='mai'+'lto:'+'lui'+'s.'+'leo'+'n@'+'iee'+'e.'+'org'; return false;">luis.<span style="display: none;">.nosp@m.</span>leon<span style="display: none;">.nosp@m.</span>@ieee<span style="display: none;">.nosp@m.</span>.org</a></li>

docs/html/md__media_lleon95_data_Personal_cynq_docs_Foundations.html

@@ -101,8 +101,8 @@
 <li>Legacy HLS -&gt; Vivado workflow</li>
 <li>Vitis Kernel workflow (newest)</li>
 </ol>
-<p>The first workflow is general and works in most of the use cases, independently if the FPGA is intended for Cloud, Edge or instrumental use (like Spartan and Artix). The key artifact is a bitstream (.bit) used for configuring the FPGA, requiring only Vitis/Vivado HLS and Vivado Design Suite.</p>
-<p>The second workflow is most specific for acceleration. It is used in modern MPSoCs and cloud-grade FPGAs. The key artifact is a binary (.xclbin) that is produced by a long chain of: Vitis HLS, Vivado Design Suite, Petalinux and Vitis. As you may notice, it's more tedious and require more tooling, consuming more storage in the development machine.</p>
+<p>The first workflow is general and works in most use cases, independently of the FPGA is intended for Cloud, Edge or instrumental use (like Spartan and Artix). The key artifact is a bitstream (.bit) used for configuring the FPGA, requiring only Vitis/Vivado HLS and Vivado Design Suite.</p>
+<p>The second workflow is most specific for acceleration. It is used in modern MPSoCs and cloud-grade FPGAs. The key artifact is a binary (.xclbin) that is produced by a long chain of: Vitis HLS, Vivado Design Suite, Petalinux and Vitis. As you may notice, it's more tedious and requires more tooling, consuming more storage in the development machine.</p>
 <p>PYNQ, particularly, has been characterised by its simplicity, only requiring the bitstream to work. It has also proved to be effective in a wide variety of boards, namely ZYNQ MPSoC and Alveo cards. In contrast, the new workflow requires more expertise in the tooling but produces better applications in terms of performance. However, the former one sacrifices a lot of the simplicity.</p>
 <h2>Our Proposal</h2>
 <p>Looking at that, we want to propose a new library based on PYNQ to allow users to code efficient C++ application while keeping the simplicity of PYNQ, allowing even more features like:</p>
@@ -119,7 +119,7 @@ <h2>Our Proposal</h2>
 <li>Complete the support for XRT interoperability.</li>
 <li>Provide a library with math kernels.</li>
 </ul>
-<p>This first release is a huge advance towards simplicity and we expect that many users look at CYNQ as the chance that they were waiting for to get started into the FPGA world, as seen in PYNQ.</p>
+<p>This first release is a huge advance towards simplicity and we expect that many users look at CYNQ as the chance that they were waiting for to get started in the FPGA world, as seen in PYNQ.</p>
 <h2>How does CYNQ work?</h2>
 <p>An application is mounted on top of an abstract interface to make the API feel agnostic. In this case, CYNQ is composed of four major components:</p>
 <ul>