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@nashif nashif commented Dec 8, 2023

Part of a large effort to unify architecture interfaces, documentation and structure.

mips/riscv use exp.h
x86 uses exception.h
others use exc.h

Making all use exception.h, this will make debugging and documentation easier, i.e. the porting guide and will not leave you wondering what is the right name to pick when introducing a new arch or port.

  • drivers: intc: manage multi-level interrupt configs
  • arch: mips: rename expection header
  • arch: riscv: rename expection header
  • arch: xtensa: rename expection header
  • arch: arm64: rename expection header
  • arch: arc: rename expection header
  • arch: arm: rename expection header
  • arch: arm: cortex_a_r: rename expection header
  • arch: arm: cortex_m: rename expection header
  • arch: arm64: rename expection header
  • arch: exception: rename header guard

dcpleung
dcpleung previously approved these changes Dec 8, 2023
@npitre
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npitre commented Dec 8, 2023

You do:

--- a/arch/arm/include/cortex_a_r/exception.h
+++ b/arch/arm/include/cortex_a_r/exception.h
@@ -11,8 +11,8 @@
  * Exception/interrupt context helpers.
  */

-#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_EXC_H_
-#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_EXC_H_
+#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_EXCEPTION_H_
+#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_EXCEPTION_H_

Maybe the AARCH32 should be removed as well.

ruuddw
ruuddw previously approved these changes Dec 11, 2023
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ok for ARC

carlescufi
carlescufi previously approved these changes Dec 11, 2023
microbuilder
microbuilder previously approved these changes Dec 11, 2023
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Rename exception header and use the same name as all architecture ports.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
@nashif nashif dismissed stale reviews from microbuilder, carlescufi, ruuddw, and dcpleung via 2196e86 December 11, 2023 12:14
@nashif nashif force-pushed the topic/arch/exceptions branch from f7819b3 to 2196e86 Compare December 11, 2023 12:14
Match guard with header file name.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
@nashif nashif force-pushed the topic/arch/exceptions branch from 2196e86 to d7c40c8 Compare December 11, 2023 14:24
@nashif nashif merged commit 552f719 into zephyrproject-rtos:main Dec 11, 2023
@nashif nashif deleted the topic/arch/exceptions branch December 11, 2023 23:22
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6 participants