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Merged
nashif merged 10 commits into from
Dec 11, 2023
Merged

arch: unify exception header naming across architectures #66325

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53abea2
arch: mips: rename expection header
nashif Dec 8, 2023
0a2a684
arch: riscv: rename expection header
nashif Dec 8, 2023
b9d3678
arch: xtensa: rename expection header
nashif Dec 8, 2023
ca636b7
arch: arm64: rename expection header
nashif Dec 8, 2023
b697774
arch: arc: rename expection header
nashif Dec 8, 2023
dc803e3
arch: arm: rename expection header
nashif Dec 8, 2023
90c0d50
arch: arm: cortex_a_r: rename expection header
nashif Dec 8, 2023
c74501e
arch: arm: cortex_m: rename expection header
nashif Dec 8, 2023
8b195aa
arch: arm64: rename expection header
nashif Dec 8, 2023
d7c40c8
arch: exception: rename header guard
nashif Dec 8, 2023
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2 changes: 1 addition & 1 deletion arch/arc/core/fatal.c
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Expand Up @@ -17,7 +17,7 @@
#include <zephyr/arch/cpu.h>
#include <zephyr/logging/log.h>
#include <kernel_arch_data.h>
#include <zephyr/arch/arc/v2/exc.h>
#include <zephyr/arch/arc/v2/exception.h>

LOG_MODULE_DECLARE(os, CONFIG_KERNEL_LOG_LEVEL);

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2 changes: 1 addition & 1 deletion arch/arm/core/userspace.S
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Expand Up @@ -12,7 +12,7 @@
#include <offsets_short.h>
#include <zephyr/syscall.h>

#include <zephyr/arch/arm/exc.h>
#include <zephyr/arch/arm/exception.h>

#if defined(CONFIG_CPU_AARCH32_CORTEX_R)
#include <zephyr/arch/cpu.h>
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6 changes: 3 additions & 3 deletions arch/arm/include/cortex_a_r/exc.h → arch/arm/include/cortex_a_r/exception.h
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Expand Up @@ -11,8 +11,8 @@
* Exception/interrupt context helpers.
*/

#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_EXC_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_EXC_H_
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_EXCEPTION_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_EXCEPTION_H_

#include <zephyr/arch/cpu.h>

Expand Down Expand Up @@ -64,4 +64,4 @@ extern void z_arm_cortex_r_svc(void);

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_A_R_EXC_H_ */
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_A_R_EXCEPTION_H_ */
8 changes: 4 additions & 4 deletions arch/arm/include/cortex_m/exc.h → arch/arm/include/cortex_m/exception.h
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Expand Up @@ -11,8 +11,8 @@
* Exception/interrupt context helpers.
*/

#ifndef ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_EXC_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_EXC_H_
#ifndef ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXCEPTION_H_
#define ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXCEPTION_H_

#include <zephyr/arch/cpu.h>

Expand All @@ -23,7 +23,7 @@
#else

#include <cmsis_core.h>
#include <zephyr/arch/arm/exc.h>
#include <zephyr/arch/arm/exception.h>
#include <zephyr/irq_offload.h>

#ifdef __cplusplus
Expand Down Expand Up @@ -200,4 +200,4 @@ bool z_arm_debug_monitor_event_error_check(void);

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_ARCH_ARM_INCLUDE_AARCH32_CORTEX_M_EXC_H_ */
#endif /* ZEPHYR_ARCH_ARM_INCLUDE_CORTEX_M_EXCEPTION_H_ */
4 changes: 2 additions & 2 deletions arch/arm/include/kernel_arch_data.h
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Expand Up @@ -26,10 +26,10 @@

#if defined(CONFIG_CPU_CORTEX_M)
#include <cortex_m/stack.h>
#include <cortex_m/exc.h>
#include <cortex_m/exception.h>
#elif defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
#include <cortex_a_r/stack.h>
#include <cortex_a_r/exc.h>
#include <cortex_a_r/exception.h>
#endif

#ifndef _ASMLANGUAGE
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2 changes: 1 addition & 1 deletion arch/arm64/core/irq_offload.c
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Expand Up @@ -11,7 +11,7 @@

#include <zephyr/kernel.h>
#include <zephyr/irq_offload.h>
#include <exc.h>
#include <exception.h>

void arch_irq_offload(irq_offload_routine_t routine, const void *parameter)
{
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6 changes: 3 additions & 3 deletions arch/arm64/include/exc.h → arch/arm64/include/exception.h
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Expand Up @@ -11,8 +11,8 @@
* Exception/interrupt context helpers.
*/

#ifndef ZEPHYR_ARCH_ARM64_INCLUDE_EXC_H_
#define ZEPHYR_ARCH_ARM64_INCLUDE_EXC_H_
#ifndef ZEPHYR_ARCH_ARM64_INCLUDE_EXCEPTION_H_
#define ZEPHYR_ARCH_ARM64_INCLUDE_EXCEPTION_H_

#include <zephyr/arch/cpu.h>

Expand All @@ -37,4 +37,4 @@ static ALWAYS_INLINE bool arch_is_in_isr(void)

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_ARCH_ARM64_INCLUDE_EXC_H_ */
#endif /* ZEPHYR_ARCH_ARM64_INCLUDE_EXCEPTION_H_ */
2 changes: 1 addition & 1 deletion arch/arm64/include/kernel_arch_data.h
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Expand Up @@ -24,7 +24,7 @@
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>

#include <exc.h>
#include <exception.h>

#ifndef _ASMLANGUAGE
#include <zephyr/kernel.h>
Expand Down
2 changes: 1 addition & 1 deletion doc/hardware/arch/arm_cortex_m.rst
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Expand Up @@ -262,7 +262,7 @@ interrupt. If the ZLI feature is enabled in Mainline Cortex-M builds (see
* Regular HW interrupts are assigned priority levels lower than SVC.

The priority level configuration in Cortex-M is implemented in
:file:`include/arch/arm/exc.h`.
:file:`include/arch/arm/exception.h`.

Locking and unlocking IRQs
--------------------------
Expand Down
2 changes: 1 addition & 1 deletion include/zephyr/arch/arc/arch.h
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Expand Up @@ -23,7 +23,7 @@
#include <zephyr/arch/common/sys_bitops.h>
#include "sys-io-common.h"

#include <zephyr/arch/arc/v2/exc.h>
#include <zephyr/arch/arc/v2/exception.h>
#include <zephyr/arch/arc/v2/irq.h>
#include <zephyr/arch/arc/v2/misc.h>
#include <zephyr/arch/arc/v2/aux_regs.h>
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2 changes: 1 addition & 1 deletion include/zephyr/arch/arc/v2/error.h
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Expand Up @@ -15,7 +15,7 @@
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_ERROR_H_

#include <zephyr/arch/arc/syscall.h>
#include <zephyr/arch/arc/v2/exc.h>
#include <zephyr/arch/arc/v2/exception.h>
#include <stdbool.h>

#ifdef __cplusplus
Expand Down
6 changes: 3 additions & 3 deletions include/zephyr/arch/arc/v2/exc.h → include/zephyr/arch/arc/v2/exception.h
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Expand Up @@ -11,8 +11,8 @@
* ARC-specific kernel exception handling interface. Included by arc/arch.h.
*/

#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_EXC_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_EXC_H_
#ifndef ZEPHYR_INCLUDE_ARCH_ARC_V2_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_ARC_V2_EXCEPTION_H_

#ifdef __cplusplus
extern "C" {
Expand Down Expand Up @@ -44,4 +44,4 @@ typedef struct _irq_stack_frame z_arch_esf_t;
#define ARC_EV_MISALIGNED 0xD
#define ARC_EV_VEC_UNIT 0xE

#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_EXC_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_ARC_V2_EXCEPTION_H_ */
2 changes: 1 addition & 1 deletion include/zephyr/arch/arm/arch.h
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Expand Up @@ -23,7 +23,7 @@
#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }

#include <zephyr/arch/arm/thread.h>
#include <zephyr/arch/arm/exc.h>
#include <zephyr/arch/arm/exception.h>
#include <zephyr/arch/arm/irq.h>
#include <zephyr/arch/arm/error.h>
#include <zephyr/arch/arm/misc.h>
Expand Down
2 changes: 1 addition & 1 deletion include/zephyr/arch/arm/asm_inline_gcc.h
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Expand Up @@ -20,7 +20,7 @@

#include <zephyr/toolchain.h>
#include <zephyr/types.h>
#include <zephyr/arch/arm/exc.h>
#include <zephyr/arch/arm/exception.h>

#if defined(CONFIG_CPU_AARCH32_CORTEX_R) || defined(CONFIG_CPU_AARCH32_CORTEX_A)
#include <zephyr/arch/arm/cortex_a_r/cpu.h>
Expand Down
6 changes: 3 additions & 3 deletions include/zephyr/arch/arm/cortex_a_r/exc.h → ...de/zephyr/arch/arm/cortex_a_r/exception.h
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Expand Up @@ -9,8 +9,8 @@
* @brief ARM AArch32 Cortex-A and Cortex-R public exception handling
*/

#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_EXCEPTION_H_

#ifdef _ASMLANGUAGE
GTEXT(z_arm_exc_exit);
Expand Down Expand Up @@ -85,4 +85,4 @@ extern void z_arm_exc_exit(bool fatal);

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_A_R_EXCEPTION_H_ */
6 changes: 3 additions & 3 deletions include/zephyr/arch/arm/cortex_m/exc.h → include/zephyr/arch/arm/cortex_m/exception.h
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Expand Up @@ -9,8 +9,8 @@
* @brief ARM AArch32 Cortex-M public exception handling
*/

#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_EXCEPTION_H_

#include <zephyr/devicetree.h>

Expand Down Expand Up @@ -129,4 +129,4 @@ extern void z_arm_exc_exit(void);

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_CORTEX_M_EXCEPTION_H_ */
2 changes: 1 addition & 1 deletion include/zephyr/arch/arm/error.h
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Expand Up @@ -16,7 +16,7 @@
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_ERROR_H_

#include <zephyr/arch/arm/syscall.h>
#include <zephyr/arch/arm/exc.h>
#include <zephyr/arch/arm/exception.h>
#include <stdbool.h>

#ifdef __cplusplus
Expand Down
10 changes: 5 additions & 5 deletions include/zephyr/arch/arm/exc.h → include/zephyr/arch/arm/exception.h
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Expand Up @@ -12,15 +12,15 @@
* arm/arch.h.
*/

#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_
#ifndef ZEPHYR_INCLUDE_ARCH_ARM_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_ARM_EXCEPTION_H_

#if defined(CONFIG_CPU_CORTEX_M)
#include <zephyr/arch/arm/cortex_m/exc.h>
#include <zephyr/arch/arm/cortex_m/exception.h>
#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
#include <zephyr/arch/arm/cortex_a_r/exc.h>
#include <zephyr/arch/arm/cortex_a_r/exception.h>
#else
#error Unknown ARM architecture
#endif /* CONFIG_CPU_CORTEX_M */

#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_EXCEPTION_H_ */
2 changes: 1 addition & 1 deletion include/zephyr/arch/arm64/arch.h
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Expand Up @@ -20,7 +20,7 @@
#include <zephyr/devicetree.h>

#include <zephyr/arch/arm64/thread.h>
#include <zephyr/arch/arm64/exc.h>
#include <zephyr/arch/arm64/exception.h>
#include <zephyr/arch/arm64/irq.h>
#include <zephyr/arch/arm64/misc.h>
#include <zephyr/arch/arm64/asm_inline.h>
Expand Down
2 changes: 1 addition & 1 deletion include/zephyr/arch/arm64/error.h
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Expand Up @@ -15,7 +15,7 @@
#define ZEPHYR_INCLUDE_ARCH_ARM64_ERROR_H_

#include <zephyr/arch/arm64/syscall.h>
#include <zephyr/arch/arm64/exc.h>
#include <zephyr/arch/arm64/exception.h>
#include <stdbool.h>

#ifdef __cplusplus
Expand Down
6 changes: 3 additions & 3 deletions include/zephyr/arch/arm64/exc.h → include/zephyr/arch/arm64/exception.h
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Expand Up @@ -11,8 +11,8 @@
* ARM-specific kernel exception handling interface. Included by arm64/arch.h.
*/

#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_EXC_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_EXC_H_
#ifndef ZEPHYR_INCLUDE_ARCH_ARM64_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_ARM64_EXCEPTION_H_

/* for assembler, only works with constants */

Expand Down Expand Up @@ -63,4 +63,4 @@ typedef struct __esf z_arch_esf_t;

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_EXC_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_ARM64_EXCEPTION_H_ */
2 changes: 1 addition & 1 deletion include/zephyr/arch/mips/arch.h
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Expand Up @@ -10,7 +10,7 @@
#define ZEPHYR_INCLUDE_ARCH_MIPS_ARCH_H_

#include <zephyr/arch/mips/thread.h>
#include <zephyr/arch/mips/exp.h>
#include <zephyr/arch/mips/exception.h>
#include <zephyr/arch/common/sys_bitops.h>
#include <zephyr/arch/common/sys_io.h>
#include <zephyr/arch/common/ffs.h>
Expand Down
8 changes: 4 additions & 4 deletions include/zephyr/arch/mips/exp.h → include/zephyr/arch/mips/exception.h
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@@ -1,13 +1,13 @@
/*
* Copyright (c) 2021 Antony Pavlov <antonynpavlov@gmail.com>
*
* based on include/arch/riscv/exp.h
* based on include/arch/riscv/exception.h
*
* SPDX-License-Identifier: Apache-2.0
*/

#ifndef ZEPHYR_INCLUDE_ARCH_MIPS_EXP_H_
#define ZEPHYR_INCLUDE_ARCH_MIPS_EXP_H_
#ifndef ZEPHYR_INCLUDE_ARCH_MIPS_EXPCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_MIPS_EXPCEPTION_H_

#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
Expand Down Expand Up @@ -58,4 +58,4 @@ typedef struct __esf z_arch_esf_t;

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_EXP_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_MIPS_EXPCEPTION_H_ */
4 changes: 2 additions & 2 deletions include/zephyr/arch/riscv/arch.h
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Expand Up @@ -16,7 +16,7 @@
#define ZEPHYR_INCLUDE_ARCH_RISCV_ARCH_H_

#include <zephyr/arch/riscv/thread.h>
#include <zephyr/arch/riscv/exp.h>
#include <zephyr/arch/riscv/exception.h>
#include <zephyr/arch/riscv/irq.h>
#include <zephyr/arch/riscv/sys_io.h>
#include <zephyr/arch/common/sys_bitops.h>
Expand All @@ -29,7 +29,7 @@
#include <soc.h>
#include <zephyr/devicetree.h>
#include <zephyr/arch/riscv/csr.h>
#include <zephyr/arch/riscv/exp.h>
#include <zephyr/arch/riscv/exception.h>

/* stacks, for RISCV architecture stack should be 16byte-aligned */
#define ARCH_STACK_PTR_ALIGN 16
Expand Down
2 changes: 1 addition & 1 deletion include/zephyr/arch/riscv/error.h
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Expand Up @@ -15,7 +15,7 @@
#define ZEPHYR_INCLUDE_ARCH_RISCV_ERROR_H_

#include <zephyr/arch/riscv/syscall.h>
#include <zephyr/arch/riscv/exp.h>
#include <zephyr/arch/riscv/exception.h>
#include <stdbool.h>

#ifdef __cplusplus
Expand Down
6 changes: 3 additions & 3 deletions include/zephyr/arch/riscv/exp.h → include/zephyr/arch/riscv/exception.h
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Expand Up @@ -12,8 +12,8 @@
* RISCV-specific kernel exception handling interface.
*/

#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_
#ifndef ZEPHYR_INCLUDE_ARCH_RISCV_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_RISCV_EXCEPTION_H_

#ifndef _ASMLANGUAGE
#include <zephyr/types.h>
Expand Down Expand Up @@ -98,4 +98,4 @@ typedef struct soc_esf soc_esf_t;

#endif /* _ASMLANGUAGE */

#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_EXP_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_RISCV_EXCEPTION_H_ */
2 changes: 1 addition & 1 deletion include/zephyr/arch/xtensa/arch.h
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Expand Up @@ -38,7 +38,7 @@
/* Xtensa GPRs are often designated by two different names */
#define sys_define_gpr_with_alias(name1, name2) union { uint32_t name1, name2; }

#include <zephyr/arch/xtensa/exc.h>
#include <zephyr/arch/xtensa/exception.h>

#ifdef __cplusplus
extern "C" {
Expand Down
6 changes: 3 additions & 3 deletions include/zephyr/arch/xtensa/exc.h → include/zephyr/arch/xtensa/exception.h
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Expand Up @@ -12,8 +12,8 @@
* arch/xtensa/arch.h.
*/

#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_EXC_H_
#define ZEPHYR_INCLUDE_ARCH_XTENSA_EXC_H_
#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_EXCEPTION_H_
#define ZEPHYR_INCLUDE_ARCH_XTENSA_EXCEPTION_H_

#ifdef __cplusplus
extern "C" {
Expand All @@ -37,4 +37,4 @@ char *z_xtensa_exccause(unsigned int cause_code);
#endif


#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_EXC_H_ */
#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_EXCEPTION_H_ */
2 changes: 1 addition & 1 deletion samples/subsys/debug/debugmon/src/main.c
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Expand Up @@ -8,7 +8,7 @@
#include <zephyr/drivers/gpio.h>
#include <zephyr/sys/printk.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/exc.h>
#include <zephyr/arch/arm/exception.h>

#define LED0_NODE DT_ALIAS(led0)
static const struct gpio_dt_spec led = GPIO_DT_SPEC_GET(LED0_NODE, gpios);
Expand Down
2 changes: 1 addition & 1 deletion soc/arm/nxp_imx/rt6xx/soc.c
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Expand Up @@ -19,7 +19,7 @@
#include <zephyr/drivers/uart.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#include <cortex_m/exc.h>
#include <cortex_m/exception.h>
#include <fsl_power.h>
#include <fsl_clock.h>
#include <fsl_common.h>
Expand Down
2 changes: 1 addition & 1 deletion soc/arm/nxp_lpc/lpc54xxx/soc.c
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Expand Up @@ -19,7 +19,7 @@
#include <zephyr/drivers/uart.h>
#include <zephyr/linker/sections.h>
#include <zephyr/arch/cpu.h>
#include <cortex_m/exc.h>
#include <cortex_m/exception.h>
#include <fsl_power.h>
#include <fsl_clock.h>
#include <fsl_common.h>
Expand Down
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