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[Draft] Add support for WCH CH32V SoC/CH32V307V-EVB-R1 board #49886
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If using GPIO without the interrupts, GPIO can work even without EXTI. Adding #ifdef guard to divide the code that depends on EXTI. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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arch/riscv/Kconfig
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I'm fine with adding this but adding weak symbols and blurring the distinction between PLIC and CLIC is something that must be justified a bit better. Why do you need this? To save some code or do you actually need this to be able to implement support for this board?
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I think it make improvement to introduce the weak symbol, but that is not mainly intention in this PR.
Rewrite it based on current code.
I consider to create another PR to introduce the weak symbol.
west.yml
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we usually do not pull directly from outside repos. See the other modules in this file.
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I need to submit it to zephyr as the new module.
I will update it after approve it.
Added HAL module for WCH devices Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This patch introduces modules/hal_wch, which contains CMakeLists.txt and Kconfig to build WCH SoCs. WCH's CH32V SoCs have STM32 compatible peripherals. Zephyr already supports GD32 peripherals, which are compatible with STM32's one. So it is possible to use the GD32 drivers for such peripherals. The HAL implements GD32 compatible layer, and It can use with the GD32 drivers. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add wch(Nanjing Qinheng Microelectronics Co., Ltd) binding prefix. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add support for the WCH QingKe core's systick timer. The timer is built-in the WCH QingKe processor core. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add support for the PFIC interrupt controller which is used with the WCH QingKe processor core. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add the condition that use the WCH PFIC interrupt controller to arch/riscv/irq.h and soc_common_irq.c. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add support for WCH CH32V307 SoC. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Add a basic support for WCH CH32V307V-EVT-R1. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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Definitely a no-go to re-use GD32 drivers. While CH devices are yet another ST clone, we can't re-use Zephyr drivers because we're using HALs underneath.
It's interesting because we could probably have generic drivers for ST/GD/CH if they were native, but definitely not with current approach. But still, these clones are not 100% equal, registers are named differently to start with...
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This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 14 days. Note, that you can always re-open a closed pull request at any time. |
Could you please point me to any specific differences or other issues that could prevent using ST peripheral drivers for these clones? |
HAL license? |
As far as I can see, HALs are licensed under 3-clause BSD. |
Right, so in theory it could be done. However, in case of GD32 for example, register names are different, and part numbers do not follow STM32, see for example the big IP differences between F403/F450. I'd only go for unified drivers if they are implemented natively, where you have freedom on how to organize code properly and account for multiple vendors differences. I doubt that ST maintainers have any interest in going that path, even though it would be nice to see. |
I think these differences could be accounted for even with current approach, at least for simple peripherals like UARTs and timers. But I agree that this path is infeasible without some degree of maintainer support. |
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Ideally, libopencm3 is a generic firmware for STM32clone, so I'd like to use it, but unfortunately the license is GPL, so I can't incorporate it into zephyr. Since the low-level HAL of STM32 is BSD licensed, It may be possible to support combined with it and 'forked' gd32 driver. |
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@soburi Hello, is this PR still working? |
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As an issue, I'm worried about how better way to make HAL, but I can't find a good approach, so I've stuck. Of course, I can solve it by simply importing the HAL provided by WCH, but I'm consider if I can create a common HAL for STM32(F103) clones. |
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I think the HAL provided by WCH should be imported directly. |
Add support for WCH CH32V307, and CH32V307V-EVB-R1 which is the evaluation board of this SoC.
Currently, Blinky and Hello World sample worked and it be able to debug and flash.
CH32V307 is built with a RISC-V core and STM32 cloned peripherals.
It is a similar configuration to GigaDevice GD32VF103.
HAL problems
I think it can use the gd32 driver by adding a modification to vendor-supplied HAL.
(Add APIs that are compatible with GD32 HAL's one.)
Or maybe good to create a "generic STM32 clone HAL".
This point will need to discuss.
OpenOCD problems
The link is OpenOCD binaries that support CH32V307.
http://file.mounriver.com/tools/MRS_Toolchain_Linux_x64_V1.50.tar.xz
The source is not officially provided.
It will probably also become a problem.
(unofficially https://github.com/kprasadvnsi/riscv-openocd-wch)
So, I think complete this PR more a little time.