[Draft] Add support for WCH CH32V SoC/CH32V307V-EVB-R1 board

boards/riscv/ch32v307v_evt_r1/Kconfig.board

@@ -0,0 +1,6 @@
+# Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_CH32V307V_EVT_R1
+	bool "WCH CH32V307V_EVT_R1"
+	depends on SOC_CH32V307

boards/riscv/ch32v307v_evt_r1/Kconfig.defconfig

@@ -0,0 +1,10 @@
+# WCH CH32V307V_EVT_R1 Board Configuration
+
+# Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+
+if BOARD_CH32V307V_EVT_R1
+
+config BOARD
+	default "ch32v307v_evt_r1" if BOARD_CH32V307V_EVT_R1
+
+endif # BOARD_CH32V307V_EVT_R1

boards/riscv/ch32v307v_evt_r1/board.cmake

@@ -0,0 +1,9 @@
+# Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+# It seems the 'reset run' command make flash failure.
+# Call 'reset halt', 'resume', and 'shutdown' before
+# 'reset run' to workarounds.
+board_runner_args(openocd "--cmd-post-verify=ch32v307v-shutdown")
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/riscv/ch32v307v_evt_r1/ch32v307v_evt_r1-pinctrl.dtsi

@@ -0,0 +1,14 @@
+/*
+ * Copyright (c) 2022 TOKITA Hiroshi
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <dt-bindings/pinctrl/ch32v30xxx-pinctrl.h>
+
+&pinctrl {
+	usart1_default: usart1_default {
+		group1 {
+			pinmux = <USART1_TX_PA9_NORMP>, <USART1_RX_PA10_NORMP>;
+		};
+	};
+};

boards/riscv/ch32v307v_evt_r1/ch32v307v_evt_r1.dts

@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <wch/ch32v307x.dtsi>
+#include "ch32v307v_evt_r1-pinctrl.dtsi"
+
+/ {
+	model = "WCH CH32V307V_EVT_R1";
+	compatible = "wch,ch32v307v_evt_r1";
+
+	chosen {
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+	};
+
+	leds {
+		compatible = "gpio-leds";
+		/*
+		 * LED1 and LED2 exists on J3 connector.
+		 * But the pin not connecting to any GPIO pins,
+		 * you need to connect LED1 pin to any GPIO pin.
+		 * This configuration is assuming that LED1 is
+		 * connected to PB13, which corresponding to
+		 * the Arduino's LED pin.
+		 */
+		led1: led1 {
+			gpios = <&gpiob 13 GPIO_ACTIVE_HIGH>;
+			label = "LED1";
+		};
+	};
+
+	aliases {
+		led0 = &led1;
+	};
+};
+
+&usart1 {
+	status = "okay";
+	current-speed = <115200>;
+	pinctrl-0 = <&usart1_default>;
+	pinctrl-names = "default";
+};
+
+&gpiob {
+	status = "okay";
+};

boards/riscv/ch32v307v_evt_r1/ch32v307v_evt_r1.yaml

@@ -0,0 +1,9 @@
+identifier: ch32v307v_evt_r1
+name: ch32v307v_evt_r1
+type: mcu
+arch: riscv32
+toolchain:
+  - zephyr
+  - xtools
+flash: 256
+ram: 64

boards/riscv/ch32v307v_evt_r1/ch32v307v_evt_r1_defconfig

@@ -0,0 +1,17 @@
+# WCH CH32V307V_EVT_R1 Board Configuration
+#
+# Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_CH32V30X=y
+CONFIG_SOC_CH32V307=y
+CONFIG_BOARD_CH32V307V_EVT_R1=y
+
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=n
+
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_GPIO=y

boards/riscv/ch32v307v_evt_r1/doc/index.rst

@@ -0,0 +1,124 @@
+.. _ch32v307v_evt_r1:
+
+WCH CH32V307V EVT R1
+####################
+
+.. image:: img/ch32v307v_evt_r1.jpg
+     :align: center
+     :alt: ch32v307v_evt_r1
+
+Overview
+********
+
+The WCH CH32V307V-EVT-R1 is a fully-featured development board.
+The board has FPU supported RISC-V processor, USB, Ethernet,
+and various and many basic peripherals.
+
+- `CH32V307V Page <http://www.wch-ic.com/products/CH32V307.html?>`_
+- `CH32V307V Datasheet Download Page <http://www.wch-ic.com/downloads/CH32V20x_30xDS0_PDF.html>`_
+- `CH32V307V Reference Manual Download Page <http://www.wch-ic.com/downloads/CH32FV2x_V3xRM_PDF.html>`_
+- `QingKe V4 Processor Manual Download Page (Chinese) <https://www.wch.cn/downloads/QingKeV4_Processor_Manual_PDF.html>`_
+- `GitHub Page (Firmware, board schematics, ...) <https://github.com/openwch/ch32v307>`_
+
+Hardware
+********
+
+- FPU supported 144MHz RISC-V processor
+- 64KB SRAM/256KB Flash
+- 80 x I/O ports
+- 3 x USART, 5 x UART
+- 2 x ADC(16 channel)
+- 2 x I2C
+- 3 x SPI
+- 2 x I2S
+- 2 x CAN
+- 2 x 12-bit DAC
+- 2 x basic 16-bit timer
+- 4 x universal 16-bit timer
+- 4 x advanced 16-bit timer
+- 1 x RTC
+- 1 x SysTick
+- 2 x Watchdog timer
+- 2 x DMA
+- 4 x Applifier
+- 1 x True random number generator
+- 1 x Digital Video Port
+- 1 x SDIO
+- 1 x USBFS(OTG)
+- 1 x USBHS
+- 1 x ETH(Gigabit Ethernet controller)
+
+Supported Features
+==================
+
+The board configuration supports the following hardware features:
+
+.. list-table::
+   :header-rows: 1
+
+   * - Peripheral
+     - Kconfig option
+     - Devicetree compatible
+   * - WCH QingKe SysTick
+     - :kconfig:option:`CONFIG_WCH_QINGKE_SYSTICK`
+     - :dtcompatible:`wch,qingke-systick`
+   * - WCH PFIC Interrupt Controller
+     - :kconfig:option:`CONFIG_WCH_PFIC`
+     - :dtcompatible:`wch,pfic`
+   * - GPIO
+     - :kconfig:option:`CONFIG_GPIO`
+     - :dtcompatible:`gd,gd32-gpio`
+   * - USART
+     - :kconfig:option:`CONFIG_SERIAL`
+     - :dtcompatible:`gd,gd32-usart`
+
+Serial Port
+===========
+
+The USART1 connects to the P9 USB connector via WCH-Link.
+Connect the USB connecter and launch a terminal application on your PC
+to show the UART message.
+
+Onboard LED
+===========
+
+The board has two onboard LEDs. But these are not connected to any GPIO pin.
+You need to connect the LED pin with any GPIO pin in connectors to light it.
+The default configuration uses PB13, the Arduino LED pin, as the LED pin.
+
+Programming and debugging
+*************************
+
+Building & Flashing
+===================
+
+You'll need OpenOCD with WCH CH32V series support to upload the application
+to the device. First, download the binaries for your OS from the
+`MounRiver Studio download page <http://mounriver.com/download>`_.
+(MounRiver Studio contains WCH CH32V supported OpenOCD binaries.)
+
+The Zephyr SDK uses a bundled version of OpenOCD by default. You can
+overwrite that behavior by adding the
+``-DOPENOCD=<path/to/riscv-openocd/bin/openocd>``
+parameter when building:
+
+Here is an example of building the :ref:`blinky-sample` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: ch32v307v_evt_r1
+   :goals: build flash
+   :gen-args: -DOPENOCD=<path/to/riscv-openocd/bin/openocd>
+
+Debugging
+=========
+
+You can debug an application in the usual way.  Here is an example for the
+:ref:`blinky-sample` application.
+
+.. zephyr-app-commands::
+   :zephyr-app: samples/basic/blinky
+   :board: ch32v307v_evt_r1
+   :maybe-skip-config:
+   :goals: debug
+   :gen-args: -DOPENOCD=<path/to/riscv-openocd/bin/openocd>

boards/riscv/ch32v307v_evt_r1/support/openocd.cfg

@@ -0,0 +1,25 @@
+# Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+adapter driver wlink
+
+wlink_set
+
+adapter speed 2000
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x00001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure  -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+set _FLASHNAME $_CHIPNAME.flash
+
+flash bank $_FLASHNAME wch_riscv 0x00000000 0 0 0 $_TARGETNAME.0
+
+proc ch32v307v-shutdown {} {
+	reset halt
+	resume
+	shutdown
+}

drivers/gpio/Kconfig.gd32

@@ -5,5 +5,6 @@ config GPIO_GD32
 	bool "GD32 GPIO driver"
 	default y
 	depends on DT_HAS_GD_GD32_GPIO_ENABLED
+	imply GD32_EXTI
 	help
 	  Enable the GD32 GPIO driver.

drivers/gpio/gpio_gd32.c

@@ -46,7 +46,9 @@ struct gpio_gd32_config {
 	struct gpio_driver_config common;
 	uint32_t reg;
 	uint16_t clkid;
+#ifdef CONFIG_GD32_EXTI
 	uint16_t clkid_exti;
+#endif
 	struct reset_dt_spec reset;
 };
 
@@ -55,6 +57,7 @@ struct gpio_gd32_data {
 	sys_slist_t callbacks;
 };
 
+#ifdef CONFIG_GD32_EXTI
 /**
  * @brief EXTI ISR callback.
  *
@@ -125,6 +128,7 @@ static int gpio_gd32_configure_extiss(const struct device *port,
 
 	return 0;
 }
+#endif
 
 static inline int gpio_gd32_configure(const struct device *port, gpio_pin_t pin,
 				      gpio_flags_t flags)
@@ -286,6 +290,7 @@ static int gpio_gd32_pin_interrupt_configure(const struct device *port,
 					     enum gpio_int_mode mode,
 					     enum gpio_int_trig trig)
 {
+#ifdef CONFIG_GD32_EXTI
 	if (mode == GPIO_INT_MODE_DISABLED) {
 		gd32_exti_disable(pin);
 		(void)gd32_exti_configure(pin, NULL, NULL);
@@ -321,6 +326,7 @@ static int gpio_gd32_pin_interrupt_configure(const struct device *port,
 	} else {
 		return -ENOTSUP;
 	}
+#endif
 
 	return 0;
 }
@@ -350,8 +356,10 @@ static int gpio_gd32_init(const struct device *port)
 
 	(void)clock_control_on(GD32_CLOCK_CONTROLLER,
 			       (clock_control_subsys_t *)&config->clkid);
+#ifdef CONFIG_GD32_EXTI
 	(void)clock_control_on(GD32_CLOCK_CONTROLLER,
 			       (clock_control_subsys_t *)&config->clkid_exti);
+#endif
 
 	(void)reset_line_toggle_dt(&config->reset);
 
@@ -365,9 +373,10 @@ static int gpio_gd32_init(const struct device *port)
 		},							       \
 		.reg = DT_INST_REG_ADDR(n),				       \
 		.clkid = DT_INST_CLOCKS_CELL(n, id),			       \
-		COND_CODE_1(DT_NODE_HAS_STATUS(SYSCFG_NODE, okay),	       \
+		IF_ENABLED(CONFIG_GD32_EXTI,				       \
+			(COND_CODE_1(DT_NODE_HAS_STATUS(SYSCFG_NODE, okay),    \
 			    (.clkid_exti = DT_CLOCKS_CELL(SYSCFG_NODE, id),),  \
-			    (.clkid_exti = DT_CLOCKS_CELL(AFIO_NODE, id),))    \
+			    (.clkid_exti = DT_CLOCKS_CELL(AFIO_NODE, id),))))  \
 		.reset = RESET_DT_SPEC_INST_GET(n),			       \
 	};								       \
 									       \

drivers/interrupt_controller/CMakeLists.txt

@@ -30,6 +30,7 @@ zephyr_library_sources_ifdef(CONFIG_INTC_ESP32C3            intc_esp32c3.c)
 zephyr_library_sources_ifdef(CONFIG_SWERV_PIC               intc_swerv_pic.c)
 zephyr_library_sources_ifdef(CONFIG_VEXRISCV_LITEX_IRQ      intc_vexriscv_litex.c)
 zephyr_library_sources_ifdef(CONFIG_NUCLEI_ECLIC            intc_nuclei_eclic.c)
+zephyr_library_sources_ifdef(CONFIG_WCH_PFIC                intc_wch_pfic.c)
 
 if(CONFIG_INTEL_VTD_ICTL)
   zephyr_library_include_directories(${ZEPHYR_BASE}/arch/x86/include)

drivers/interrupt_controller/Kconfig

@@ -81,4 +81,6 @@ source "drivers/interrupt_controller/Kconfig.gd32_exti"
 
 source "drivers/interrupt_controller/Kconfig.plic"
 
+source "drivers/interrupt_controller/Kconfig.pfic"
+
 endmenu

drivers/interrupt_controller/Kconfig.pfic

@@ -0,0 +1,9 @@
+# Copyright (c) 2022 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
+# SPDX-License-Identifier: Apache-2.0
+
+config WCH_PFIC
+	bool "Enhanced Core Local Interrupt Controller (ECLIC)"
+	default y
+	depends on DT_HAS_WCH_PFIC_ENABLED
+	help
+	  Interrupt controller for Nuclei SoC core.