RISC-V: Add base instruction set multilibs #5
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This commit adds the following base instruction set multilibs that can be used for every practical extension permutation: * rv32i_zicsr_zifencei * rv32e_zicsr_zifencei * rv64i_zicsr_zifencei These base instruction set multilibs are mapped to the compatible extension permutations that do not have a dedicated multilib in order to increase the ISA coverage of the toolchain. Note that the Zicsr and Zifencei extensions are still specified for the base instruction set multilibs because the Zephyr RISC-V architecture port requires them and it is not practical to configure a RISC-V core that does not support these instruction sets. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
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…te value is greater than zephyrproject-rtos#5 and optimization is -OS, the compiler will generate shift operation using loop. Changelog 2013-11-26 David Holsgrove <david.holsgrove@xilinx.com> * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove <david.holsgrove@xilinx.com> * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. Signed-off-by:Nagaraju <nmekala@xilix.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com>
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…te value is greater than zephyrproject-rtos#5 and optimization is -OS, the compiler will generate shift operation using loop. Changelog 2013-11-26 David Holsgrove <david.holsgrove@xilinx.com> * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove <david.holsgrove@xilinx.com> * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. Upstream-Status: Pending Signed-off-by:Nagaraju <nmekala@xilix.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com>
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…moddi3 function as the existing implementation is buggy" This reverts commit ebc0b98. Signed-off-by: Alp Sayin <alpsayin@gmail.com> LOCAL]: Testsuite - builtins tests require fpic Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Conflicts: gcc/testsuite/gcc.c-torture/execute/builtins/builtins.exp Signed-off-by: Alp Sayin <alpsayin@gmail.com> Quick fail g++.dg/opt/memcpy1.C This particular testcase fails with a timeout. Instead, fail it at compile-time for microblaze. This speeds up the testsuite without removing it from the FAIL reports. Upstream-Status: Pending Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> For dejagnu static testing on qemu, suppress warnings about multiple definitions from the test function and libc in line with method used by powerpc. Dynamic linking and using a qemu binary which understands sysroot resolves all test failures with builtins Upstream-Status: Pending Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Add MicroBlaze to target-supports for atomic buil. .tin tests MicroBlaze added to supported targets for atomic builtin tests. Changelog/testsuite 2014-02-14 David Holsgrove <david.holsgrove@xilinx.com> * gcc/testsuite/lib/target-supports.exp: Add microblaze to check_effective_target_sync_int_long. Upstream-Status: Pending Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Update MicroBlaze strings test for new scan-assembly output resulting in use of $LC label ChangeLog/testsuite 2014-02-14 David Holsgrove <david.holsgrove@xilinx.com> * gcc/testsuite/gcc.target/microblaze/others/strings1.c: Update to include $LC label. Upstream-Status: Pending Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Allow MicroBlaze .weakext pattern in regex match Extend regex pattern to include optional ext at the end of .weak to match the MicroBlaze weak label .weakext ChangeLog/testsuite 2014-02-14 David Holsgrove <david.holsgrove@xilinx.com> * gcc/testsuite/g++.dg/abi/rtti3.C: Extend scan-assembler pattern to take optional ext after .weak. * gcc/testsuite/g++.dg/abi/thunk4.C: Likewise. Upstream-Status: Pending Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Conflicts: gcc/testsuite/g++.dg/abi/rtti3.C Signed-off-by: Alp Sayin <alpsayin@gmail.com> Add MicroBlaze to check_profiling_available Testsuite, add microblaze*-*-* target in check_profiling_available inline with other archs setting profiling_available_saved to 0 Upstream-Status: Pending Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fix atomic side effects. In atomic_compare_and_swapsi, add side effects to prevent incorrect assumptions during optimization. Previously, the outputs were considered unused; this generated assembly code with undefined side effects after invocation of the atomic. Upstream-Status: Pending Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Conflicts: gcc/config/microblaze/microblaze.md Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fix atomic boolean return value. In atomic_compare_and_swapsi, fix boolean return value. Previously, it contained zero if successful and non-zero if unsuccessful. Upstream-Status: Pending Signed-off-by: Kirk Meyer <kirk.meyer@sencore.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fix the Microblaze crash with msmall-divides flag Compiler is crashing when we use msmall-divides and mxl-barrel-shift flag. This is because when use above flags microblaze_expand_divide function will be called for division operation. In microblaze_expand_divide function we are using sub_reg but MicroBlaze doesn't have subreg register due to this compiler was crashing. Changed the logic to avoid sub_reg call Upstream-Status: Pending Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> Conflicts: gcc/config/microblaze/microblaze.c Signed-off-by: Alp Sayin <alpsayin@gmail.com> Added ashrsi3_with_size_opt Added ashrsi3_with_size_opt pattern to optimize the sra instructions when the -Os optimization is used. lshrsi3_with_size_opt is being removed as it has conflicts with unsigned int variables Upstream-Status: Pending Signed-off-by:Nagaraju Mekala <nmekala@xilix.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Use bralid for profiler calls Signed-off-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Removed moddi3 routinue Using the default moddi3 function as the existing implementation has many bugs Upstream-Status: Pending Signed-off-by:Nagaraju <nmekala@xilix.com> Conflicts: libgcc/config/microblaze/moddi3.S Signed-off-by: Alp Sayin <alpsayin@gmail.com> Add INIT_PRIORITY support Added TARGET_ASM_CONSTRUCTOR and TARGET_ASM_DESTRUCTOR macros. These macros allows users to control the order of initialization of objects defined at namespace scope with the init_priority attribute by specifying a relative priority, a constant integral expression currently bounded between 101 and 65535 inclusive. Lower numbers indicate a higher priority. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Add optimized lshrsi3 When barrel shifter is not present, the immediate value is greater than zephyrproject-rtos#5 and optimization is -OS, the compiler will generate shift operation using loop. Changelog 2013-11-26 David Holsgrove <david.holsgrove@xilinx.com> * gcc/config/microblaze/microblaze.md: Add size optimized lshrsi3 insn ChangeLog/testsuite 2014-02-12 David Holsgrove <david.holsgrove@xilinx.com> * gcc/testsuite/gcc.target/microblaze/others/lshrsi_Os_1.c: New test. Upstream-Status: Pending Signed-off-by:Nagaraju <nmekala@xilix.com> Signed-off-by: David Holsgrove <david.holsgrove@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Add cbranchsi4_reg This patch optimizes the generation of pcmpne/pcmpeq instruction if the compare instruction has no immediate values.For the immediate values the xor instruction is generated Upstream-Status: Pending Signed-off-by: Nagaraju Mekala <nmekala@xilix.com> Signed-off-by: Ajit Agarwal <ajitkum@xilinx.com> ChangeLog: 2015-01-13 Nagaraju Mekala <nmekala@xilix.com> Ajit Agarwal <ajitkum@xilinx.com> *microblaze.md (cbranchsi4_reg): New *microblaze.c (microblaze_expand_conditional_branch_reg): New Conflicts: gcc/config/microblaze/microblaze-protos.h Signed-off-by: Alp Sayin <alpsayin@gmail.com> Inline Expansion of fsqrt builtin. The changes are made in the patch for the inline expansion of the fsqrt builtin with fqrt instruction. The sqrt math function takes double as argument and return double as argument. The pattern is selected while expanding the unary op through expand_unop which passes DFmode and the DFmode pattern was not there returning zero. Thus the sqrt math function is not inlined and expanded. The pattern with DFmode argument is added. Also the source and destination argument is not same the DF through two different consecutive registers with lower 32 bit is the argument passed to sqrt and the higher 32 bit is zero. If the source and destinations are different the DFmode 64 bits registers is not set properly giving the problem in runtime. Such changes are taken care in the implementation of the pattern for DFmode for inline expansion of the sqrt. ChangeLog: 2015-06-16 Ajit Agarwal <ajitkum@xilinx.com> Nagaraju Mekala <nmekala@xilinx.com> * config/microblaze/microblaze.md (sqrtdf2): New pattern. Upstream-Status: Pending Signed-off-by:Ajit Agarwal ajitkum@xilinx.com Nagaraju Mekala nmekala@xilinx.com Signed-off-by: Alp Sayin <alpsayin@gmail.com> microblaze.md: Improve 'adddi3' and 'subdi3' insn definitions Change adddi3 to handle DI immediates as the second operand, this requires modification to the output template however reduces the need to specify seperate templates for 16-bit positive/negative immediate operands. The use of 32-bit immediates for the addi and addic instructions is handled by the assembler, which will emit the imm instructions when required. This conveniently handles the optimizable cases where the immediate constant value does not need the higher half words of the operands upper/lower words. Change the constraints of the subdi3 instruction definition such that it does not match the second operand as an immediate value. This is because there is no definition to handle this case nor is it possible to implement purely with instructions as microblaze does not provide an instruction to perform a forward arithmetic subtraction (it only provides reverse 'rD = IMM - rA'). Upstream-Status: Pending Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Update ashlsi3 & movsf patterns This patch removes the use of HOST_WIDE_INT_PRINT_HEX macro in print_operand of ashlsi3_with_mul_nodelay,ashlsi3_with_mul_delay and movsf_internal patterns beacuse HOST_WIDE_INT_PRINT_HEX is generating 64-bit value which our instruction doesn't support so using gen_int_mode function Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> :Ajit Agarwal <ajitkum@xilinx.com> ChangeLog: 2016-01-07 Nagaraju Mekala <nmekala@xilix.com> Ajit Agarwal <ajitkum@xilinx.com> *microblaze.md (ashlsi3_with_mul_nodelay, ashlsi3_with_mul_delay, movsf_internal): Updated the patterns to use gen_int_mode function *microblaze.cc (print_operand): updated the 'F' case to use "unsinged int" instead of HOST_WIDE_INT_PRINT_HEX Conflicts: gcc/config/microblaze/microblaze.c Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> 8-stage pipeline for microblaze This patch adds the support for the 8-stage pipeline. The new 8-stage pipeline reduces the latencies of float & integer division drastically Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Correct the const high double immediate value with this patch the loading of the DI mode immediate values will be using REAL_VALUE_FROM_CONST_DOUBLE and REAL_VALUE_TO_TARGET_DOUBLE functions, as CONST_DOUBLE_HIGH was returning the sign extension value even of the unsigned long long constants also Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> Ajit Agarwal <ajitkum@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fix internal compiler error with msmall-divides This patch will fix the internal error microblaze_expand_divide function which come of rtx PLUS where the mem_rtx is of type SI and the operand is of type QImode. This patch modifies the mem_rtx as QImode and Plus as QImode to fix the error. Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> Ajit Agarwal <ajitkum@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fix the calculation of high word in a long long 64-bit This patch will change the calculation of high word in a long long 64-bit. Earlier to this patch the high word of long long word (0xF0000000ULL) is coming to be 0xFFFFFFFF and low word is 0xF0000000. Instead the high word should be 0x00000000 and the low word should be 0xF0000000. This patch removes the condition of checking high word = 0 & low word < 0. This check is not required for the correctness of calculating 32-bit high and low words in a 64-bit long long. Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> Ajit Agarwal <ajitkum@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> this patch has 1.Fixed the bug in version calculation. 2.Add new bitfield instructions. Signed-off-by :Mahesh Bodapati <mbodapat@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fixing the issue with the builtin_alloc. register r18 was not properly handling the stack pattern which was resolved by using free available register signed-off-by:nagaraju mekala <nmekala@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Removed fsqrt generation for double values. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Intial commit of 64-bit Microblaze Conflicts: gcc/config/microblaze/microblaze.md Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Intial commit for 64bit-MB sources. Need to cleanup the code later. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> re-arrangement of the compare branches Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> previous commit broke the handling of SI Branch compare for Microblaze 32-bit.. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Support of multilibs with m64 ... Conflicts: gcc/config/microblaze/microblaze-c.c signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fixed issues like: 1 Interrupt alignment issue 2 Sign extension issue Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> fixed below issues: - Floating point print issues in 64bit mode - Dejagnu Jump related issues - Added dbl instruction Conflicts: gcc/config/microblaze/microblaze.md Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> -Added double arith instructions -Fixed prologue stack pointer decrement issue Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fixed the issue in the delay slot with swap instructions Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fixed the load store issue with the 32bit arith libraries Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> extending the Dwarf support to 64bit Microblaze Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> fixing the typo errors in umodsi3 file Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> fixing the 32bit LTO related issue9(1014024) Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fixed the missing stack adjustment in prologue of modsi3 function Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> corrected SPN for dlong instruction mapping. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> fixing the long & long long mingw toolchain issue Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fix the MB-64 bug of handling QI objects Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> We will check the possibility of peephole2 optimization,if we can then we will fix the compiler issue. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> fixed typos in mul,div and mod assembly files. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> MB-64 removal of barrel-shift instructions from default By default MB-64 is generatting barrel-shift instructions. It has been removed from default. Barrel-shift instructions will be generated only if barrel-shifter is enabled. Similarly to double instructions as well. Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Added new MB-64 single register arithmetic instructions Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Added support for 64 bit Immediate values. Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Fix Compiler crash with -freg-struct-return This patch fixes a bug in MB GCC regarding the passing struct values in registers. Currently we are only handling SImode With this patch all other modes are handled properly Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Add TARGET_OPTION_OPTIMIZATION and disable fivopts by default Added TARGET_OPTION_OPTIMIZATIONS and Turn off ivopts by default. * gcc/common/config/microblaze/microblaze-common.c (microblaze_option_optimization_table): Disable fivopts by default. Upstream-Status: Pending Signed-off-by: Nagaraju Mekala <nmekala@xilinx.com> Mahesh Bodapati <mbodapat@xilinx.com> Conflicts: gcc/common/config/microblaze/microblaze-common.c Conflicts: gcc/common/config/microblaze/microblaze-common.c Signed-off-by: Alp Sayin <alpsayin@gmail.com> Reducing Stack space for arguments Currently in Microblaze target stack space for arguments in register is being allocated even if there are no arguments in the function. This patch will optimize the extra 24 bytes that are being allocated. Signed-off-by :Nagaraju Mekala <nmekala@xilix.com> :Ajit Agarwal <ajitkum@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> If we use break_handler attribute then interrupt vector call happened to break_handler instead of interrupt_handler. this fix will resolve the issue CR-1081780. This fix will not change the behavior of compiler unless there is a usage of break_handler attribute. signed-off-by : Mahesh Bodapati <mbodapat@xilinx.com> Upstream-Status: Pending Signed-off-by: Mark Hatle <mark.hatle@amd.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com> Add Zero_extended instructions Due to latest changes in GCC-10.2 MB64 perforamance has reduced We have added zero_extended instructions to get rid of left shift and right shift loops [CR/TSR]: TSR-974519 Upstream-Status: Pending Signed-off-by: Nagaraju Mekala<nmekala@xilinx.com> Mahesh Bodapati<mbodapat@xilinx.com> Signed-off-by: Alp Sayin <alpsayin@gmail.com>
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…o_debug_section [PR116614]
cat abc.C
#define A(n) struct T##n {} t##n;
#define B(n) A(n##0) A(n##1) A(n##2) A(n##3) A(n##4) A(n##5) A(n##6) A(n##7) A(n##8) A(n##9)
#define C(n) B(n##0) B(n##1) B(n##2) B(n##3) B(n##4) B(n##5) B(n##6) B(n##7) B(n##8) B(n##9)
#define D(n) C(n##0) C(n##1) C(n##2) C(n##3) C(n##4) C(n##5) C(n##6) C(n##7) C(n##8) C(n##9)
#define E(n) D(n##0) D(n##1) D(n##2) D(n##3) D(n##4) D(n##5) D(n##6) D(n##7) D(n##8) D(n##9)
E(1) E(2) E(3)
int main () { return 0; }
./xg++ -B ./ -o abc{.o,.C} -flto -flto-partition=1to1 -O2 -g -fdebug-types-section -c
./xgcc -B ./ -o abc{,.o} -flto -flto-partition=1to1 -O2
(not included in testsuite as it takes a while to compile) FAILs with
lto-wrapper: fatal error: Too many copied sections: Operation not supported
compilation terminated.
/usr/bin/ld: error: lto-wrapper failed
collect2: error: ld returned 1 exit status
The following patch fixes that. Most of the 64K+ section support for
reading and writing was already there years ago (and especially reading used
quite often already) and a further bug fixed in it in the PR104617 fix.
Yet, the fix isn't solely about removing the
if (new_i - 1 >= SHN_LORESERVE)
{
*err = ENOTSUP;
return "Too many copied sections";
}
5 lines, the missing part was that the function only handled reading of
the .symtab_shndx section but not copying/updating of it.
If the result has less than 64K-epsilon sections, that actually wasn't
needed, but e.g. with -fdebug-types-section one can exceed that pretty
easily (reported to us on WebKitGtk build on ppc64le).
Updating the section is slightly more complicated, because it basically
needs to be done in lock step with updating the .symtab section, if one
doesn't need to use SHN_XINDEX in there, the section should (or should be
updated to) contain SHN_UNDEF entry, otherwise needs to have whatever would
be overwise stored but couldn't fit. But repeating due to that all the
symtab decisions what to discard and how to rewrite it would be ugly.
So, the patch instead emits the .symtab_shndx section (or sections) last
and prepares the content during the .symtab processing and in a second
pass when going just through .symtab_shndx sections just uses the saved
content.
2024-09-07 Jakub Jelinek <jakub@redhat.com>
PR lto/116614
* simple-object-elf.c (SHN_COMMON): Align comment with neighbouring
comments.
(SHN_HIRESERVE): Use uppercase hex digits instead of lowercase for
consistency.
(simple_object_elf_find_sections): Formatting fixes.
(simple_object_elf_fetch_attributes): Likewise.
(simple_object_elf_attributes_merge): Likewise.
(simple_object_elf_start_write): Likewise.
(simple_object_elf_write_ehdr): Likewise.
(simple_object_elf_write_shdr): Likewise.
(simple_object_elf_write_to_file): Likewise.
(simple_object_elf_copy_lto_debug_section): Likewise. Don't fail for
new_i - 1 >= SHN_LORESERVE, instead arrange in that case to copy
over .symtab_shndx sections, though emit those last and compute their
section content when processing associated .symtab sections. Handle
simple_object_internal_read failure even in the .symtab_shndx reading
case.
(cherry picked from commit bb8dd09)
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This commit adds the following base instruction set multilibs that can
be used for every practical extension permutation:
These base instruction set multilibs are mapped to the compatible
extension permutations that do not have a dedicated multilib in order
to increase the ISA coverage of the toolchain.
Note that the Zicsr and Zifencei extensions are still specified for the
base instruction set multilibs because the Zephyr RISC-V architecture
port requires them and it is not practical to configure a RISC-V core
that does not support these instruction sets.
Signed-off-by: Stephanos Ioannidis root@stephanos.io