Flip serial_tl_clock to be generated off-chip

[jerryz123]

Previously, the serial_tl_clock is generated on-chip, and passed to the host bringup FPGA. This flips that, so the FPGA must generate the clock.

Follows up on #1435 to improve the serial_tl robustness and ease-of-use.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

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[jerryz123]

@harrisonliew You are right, the constraints for the existing vcu118 bringup flow should add a clock input into the chip.

However, doing so would cause backwards compatibility issues with anyone who uses that bringup flow for existing chips. And future chips should use a lightweight bringup platform that is yet-to-be implemented anyways.

Can we just leave the existing vcu118 setup as is, until the new one is brought up?

@abejgonzalez @harrisonliew what do you think?

[harrisonliew]

Can we just leave the existing vcu118 setup as is, until the new one is brought up?

I'm fine with this if either 1) the clock direction is selectable (e.g. via a legacy vs. new VCU118 config) or 2) the VCU118 bringup is explicitly disallowed in the documentation for bringup of chips built using Chipyard version >=1.9.1.

[abejgonzalez]

I'm fine with deprecating the current VCU118 bringup flow and just adding to the docs "Hey don't use this for future chips use XYZ flow"

[abejgonzalez]

LGTM

[jerryz123]

I've realized supporting bidirectional clock is very useful.
This PR will flip the default to be generate-off-clock.
The next PR will add support for bidirectional clock.