Improve readability for vcu118 fpga code

fpga/src/main/scala/vcu118/HarnessBinders.scala

@@ -14,32 +14,26 @@ import chipyard.harness.{OverrideHarnessBinder}
 
 /*** UART ***/
 class WithUART extends OverrideHarnessBinder({
-  (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
-    th match { case vcu118th: VCU118FPGATestHarnessImp => {
-      vcu118th.vcu118Outer.io_uart_bb.bundle <> ports.head
-    } }
+  (system: HasPeripheryUARTModuleImp, th: VCU118FPGATestHarness, ports: Seq[UARTPortIO]) => {
+    th.io_uart_bb.bundle <> ports.head
   }
 })
 
 /*** SPI ***/
 class WithSPISDCard extends OverrideHarnessBinder({
-  (system: HasPeripherySPI, th: BaseModule with HasHarnessSignalReferences, ports: Seq[SPIPortIO]) => {
-    th match { case vcu118th: VCU118FPGATestHarnessImp => {
-      vcu118th.vcu118Outer.io_spi_bb.bundle <> ports.head
-    } }
+  (system: HasPeripherySPI, th: VCU118FPGATestHarness, ports: Seq[SPIPortIO]) => {
+    th.io_spi_bb.bundle <> ports.head
   }
 })
 
 /*** Experimental DDR ***/
 class WithDDRMem extends OverrideHarnessBinder({
-  (system: CanHaveMasterTLMemPort, th: BaseModule with HasHarnessSignalReferences, ports: Seq[HeterogeneousBag[TLBundle]]) => {
-    th match { case vcu118th: VCU118FPGATestHarnessImp => {
-      require(ports.size == 1)
-
-      val bundles = vcu118th.vcu118Outer.ddrClient.out.map(_._1)
-      val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
-      bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
-      ddrClientBundle <> ports.head
-    } }
+  (system: CanHaveMasterTLMemPort, th: VCU118FPGATestHarness, ports: Seq[HeterogeneousBag[TLBundle]]) => {
+    require(ports.size == 1)
+
+    val bundles = th.ddrClient.out.map(_._1)
+    val ddrClientBundle = Wire(new HeterogeneousBag(bundles.map(_.cloneType)))
+    bundles.zip(ddrClientBundle).foreach { case (bundle, io) => bundle <> io }
+    ddrClientBundle <> ports.head
   }
 })

fpga/src/main/scala/vcu118/TestHarness.scala

@@ -88,50 +88,45 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
   ddrNode := ddrClient
 
   // module implementation
-  override lazy val module = new VCU118FPGATestHarnessImp(this)
-}
+  override lazy val module = new LazyRawModuleImp(this) with HasHarnessSignalReferences {
+    val reset = IO(Input(Bool()))
+    xdc.addPackagePin(reset, "L19")
+    xdc.addIOStandard(reset, "LVCMOS12")
 
-class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessSignalReferences {
+    val resetIBUF = Module(new IBUF)
+    resetIBUF.io.I := reset
 
-  val vcu118Outer = _outer
+    val sysclk: Clock = sysClkNode.out.head._1.clock
 
-  val reset = IO(Input(Bool()))
-  _outer.xdc.addPackagePin(reset, "L19")
-  _outer.xdc.addIOStandard(reset, "LVCMOS12")
+    val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
+    sdc.addAsyncPath(Seq(powerOnReset))
 
-  val resetIBUF = Module(new IBUF)
-  resetIBUF.io.I := reset
-
-  val sysclk: Clock = _outer.sysClkNode.out.head._1.clock
-
-  val powerOnReset: Bool = PowerOnResetFPGAOnly(sysclk)
-  _outer.sdc.addAsyncPath(Seq(powerOnReset))
+    val ereset: Bool = chiplink.get() match {
+      case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n
+      case _ => false.B
+    }
 
-  val ereset: Bool = _outer.chiplink.get() match {
-    case Some(x: ChipLinkVCU118PlacedOverlay) => !x.ereset_n
-    case _ => false.B
-  }
+    pllReset := (resetIBUF.io.O || powerOnReset || ereset)
 
-  _outer.pllReset := (resetIBUF.io.O || powerOnReset || ereset)
+    // reset setup
+    val hReset = Wire(Reset())
+    hReset := dutClock.in.head._1.reset
 
-  // reset setup
-  val hReset = Wire(Reset())
-  hReset := _outer.dutClock.in.head._1.reset
+    val buildtopClock = dutClock.in.head._1.clock
+    val buildtopReset = WireInit(hReset)
+    val dutReset = hReset.asAsyncReset
+    val success = false.B
 
-  val buildtopClock = _outer.dutClock.in.head._1.clock
-  val buildtopReset = WireInit(hReset)
-  val dutReset = hReset.asAsyncReset
-  val success = false.B
+    childClock := buildtopClock
+    childReset := buildtopReset
 
-  childClock := buildtopClock
-  childReset := buildtopReset
+    // harness binders are non-lazy
+    topDesign match { case d: HasIOBinders =>
+      ApplyHarnessBinders(this, d.lazySystem, d.portMap)
+    }
 
-  // harness binders are non-lazy
-  _outer.topDesign match { case d: HasIOBinders =>
-    ApplyHarnessBinders(this, d.lazySystem, d.portMap)
+    // check the top-level reference clock is equal to the default
+    // non-exhaustive since you need all ChipTop clocks to equal the default
+    require(getRefClockFreq == p(DefaultClockFrequencyKey))
   }
-
-  // check the top-level reference clock is equal to the default
-  // non-exhaustive since you need all ChipTop clocks to equal the default
-  require(getRefClockFreq == p(DefaultClockFrequencyKey))
-}
+}

fpga/src/main/scala/vcu118/bringup/HarnessBinders.scala

@@ -18,53 +18,45 @@ import chipyard.harness.{ComposeHarnessBinder, OverrideHarnessBinder}
 
 /*** UART ***/
 class WithBringupUART extends ComposeHarnessBinder({
-  (system: HasPeripheryUARTModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[UARTPortIO]) => {
-    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
-      require(ports.size == 2)
+  (system: HasPeripheryUARTModuleImp, th: BringupVCU118FPGATestHarness, ports: Seq[UARTPortIO]) => {
+    require(ports.size == 2)
 
-      vcu118th.bringupOuter.io_fmc_uart_bb.bundle <> ports.last
-    } }
+    th.io_fmc_uart_bb.bundle <> ports.last
   }
 })
 
 /*** I2C ***/
 class WithBringupI2C extends OverrideHarnessBinder({
-  (system: HasPeripheryI2CModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[I2CPort]) => {
-    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
-      require(ports.size == 1)
+  (system: HasPeripheryI2CModuleImp, th: BringupVCU118FPGATestHarness, ports: Seq[I2CPort]) => {
+    require(ports.size == 1)
 
-      vcu118th.bringupOuter.io_i2c_bb.bundle <> ports.head
-    } }
+    th.io_i2c_bb.bundle <> ports.head
   }
 })
 
 /*** GPIO ***/
 class WithBringupGPIO extends OverrideHarnessBinder({
-  (system: HasPeripheryGPIOModuleImp, th: BaseModule with HasHarnessSignalReferences, ports: Seq[GPIOPortIO]) => {
-    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
-      (vcu118th.bringupOuter.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
-        bb_io.bundle <> dut_io
-      }
-    } }
+  (system: HasPeripheryGPIOModuleImp, th: BringupVCU118FPGATestHarness, ports: Seq[GPIOPortIO]) => {
+    (th.io_gpio_bb zip ports).map { case (bb_io, dut_io) =>
+      bb_io.bundle <> dut_io
+    }
   }
 })
 
 /*** TSI Host Widget ***/
 class WithBringupTSIHost extends OverrideHarnessBinder({
-  (system: HasPeripheryTSIHostWidget, th: BaseModule with HasHarnessSignalReferences, ports: Seq[Data]) => {
-    th match { case vcu118th: BringupVCU118FPGATestHarnessImp => {
-      require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link
-
-      ports.head match { case tlPort: HeterogeneousBag[TLBundle] =>
-        val tsiBundles = vcu118th.bringupOuter.tsiDdrClient.out.map(_._1)
-        val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
-        tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
-        tsiDdrClientBundle <> tlPort
-      }
-
-      ports.last match { case serialPort: TSIHostWidgetIO =>
-        vcu118th.bringupOuter.io_tsi_serial_bb.bundle <> serialPort
-      }
-    } }
+  (system: HasPeripheryTSIHostWidget, th: BringupVCU118FPGATestHarness, ports: Seq[Data]) => {
+    require(ports.size == 2) // 1st goes to the TL mem, 2nd goes to the serial link
+
+    ports.head match { case tlPort: HeterogeneousBag[TLBundle] =>
+      val tsiBundles = th.tsiDdrClient.out.map(_._1)
+      val tsiDdrClientBundle = Wire(new HeterogeneousBag(tsiBundles.map(_.cloneType)))
+      tsiBundles.zip(tsiDdrClientBundle).foreach { case (bundle, io) => bundle <> io }
+      tsiDdrClientBundle <> tlPort
+    }
+
+    ports.last match { case serialPort: TSIHostWidgetIO =>
+      th.io_tsi_serial_bb.bundle <> serialPort
+    }
   }
 })

fpga/src/main/scala/vcu118/bringup/TestHarness.scala

@@ -19,7 +19,7 @@ import sifive.blocks.devices.gpio._
 
 import testchipip.{HasPeripheryTSIHostWidget, PeripheryTSIHostKey, TSIHostWidgetIO, TLSinkSetter}
 
-import chipyard.fpga.vcu118.{VCU118FPGATestHarness, VCU118FPGATestHarnessImp, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
+import chipyard.fpga.vcu118.{VCU118FPGATestHarness, DDR2VCU118ShellPlacer, SysClock2VCU118ShellPlacer}
 
 import chipyard.{ChipTop}
 
@@ -90,11 +90,4 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
     := TLAtomicAutomata(passthrough=false)
     := TLSinkSetter(64)
     := tsiDdrClient)
-
-  // module implementation
-  override lazy val module = new BringupVCU118FPGATestHarnessImp(this)
-}
-
-class BringupVCU118FPGATestHarnessImp(_outer: BringupVCU118FPGATestHarness) extends VCU118FPGATestHarnessImp(_outer) {
-  lazy val bringupOuter = _outer
 }