Improve readability for vcu118 fpga code

[Lorilandly]

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you update the conda .conda-lock.yml file if you updated the conda requirements file?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

This pr rewrites some of the code for vcu118. No new or breaking changes.

[jerryz123]

Many improvements here. Thanks!

[Lorilandly]

@jerryz123 No problem!
Mind looking at chipsalliance/rocket-chip-fpga-shells#7 any time? I'm trying to port chipyard for vc707 and this fix is needed.

[Lorilandly]

I have again reviewed this PR and found that it doesn't really work and it will break the support. To be exact, after this patch, many connections between chiptop and mig disappears, and the signals for sdio and uart gets shorted. I'm really not sure why this is happening.