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Add support for NoC based interconnect with Constellation #1224
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@@ -21,3 +21,4 @@ env-riscv-tools.sh | |
env-esp-tools.sh | ||
.bsp/ | ||
.conda-env/ | ||
.#* |
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SoCs with NoC-based Interconnects | ||
================================== | ||
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The primary way to integrate a network-on-chip into a Chipyard SoC is to map one of the standard TileLink crossbar-based buses (System Bus, Memory Bus, Control Bus, etc.) to a Constellation-generated NoC. | ||
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The interconnect can be mapped as a "private" interconnect for the TileLink bus, in which case a dedicated interconnect to carry the bus traffic will be generated. | ||
Alternatively, the interconnect can be mapped to a shared global interconnect, in which case multiple TileLink buses can be transported over a single shared interconnect. | ||
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Private Interconnects | ||
--------------------- | ||
An example of integrating dedicated private interconnects for the System Bus, Memory Bus, and Control Bus can be seen in the ``MultiNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/config/NoCConfigs.scala>`__. | ||
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.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala | ||
:language: scala | ||
:start-after: DOC include start: MultiNoCConfig | ||
:end-before: DOC include end: MultiNoCConfig | ||
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Note that for each bus (``Sbus`` / ``Mbus`` / ``Cbus``), the configuration fragment provides both a parameterization of the private NoC, as well as a mapping between TileLink agents and physical NoC nodes. | ||
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For more information on how to construct the NoC parameters, see the `Constellation documentation <http://constellation.readthedocs.io>`__. | ||
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Shared Global Interconnect | ||
--------------------------- | ||
An example of integrating a single global interconnect that supports transporting multiple TileLink buses can be seen in the ``SharedNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/config/NoCConfigs.scala>`__. | ||
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.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala | ||
:language: scala | ||
:start-after: DOC include start: SharedNoCConfig | ||
:end-before: DOC include end: SharedNoCConfig | ||
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Note that for each bus, the configuration fragment provides only the mapping between TileLink agents and physical NoC nodes, while a separate fragement provides the configuration for the global interconnect. | ||
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For more information on how to construct the NoC parameters, see the `Constellation documentation <http://constellation.readthedocs.io>`__. |
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Constellation | ||
======================== | ||
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.. image:: ../_static/images/bigsoc.svg | ||
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`Constellation <https://github.com/ucb-bar/constellation>`__ is a Chisel NoC RTL generator framework designed from the ground up to support integration in a heterogeneous SoC and evaluation of highly irregular NoC architectures. | ||
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- Constellation generates **packet-switched wormhole-routed networks with virtual networks and credit-based flow control** | ||
- Constellation supports **arbitrary directed graph network topologies**, including **irregular** and **hierarchical** network topologies | ||
- Constellation includes a **routing algorithm verifier and routing-table compiler**, which can verify and generate deadlock-free routing tables for arbitrary topologies | ||
- Constellation is a **protocol-independent transport layer**, yet is capable of compliant deadlock-free transport of protocols like **AXI-4** and **TileLink** | ||
- Constellation supports drop-in **integration in Chipyard/Rocketchip SoCs** | ||
- Constellation is **rigorously tested**, with almost 100 different tests across as many network configurations | ||
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Constellation is fully integrated into Chipyard, and can be used to generate almost any interconnect in a Chipyard/Rocketchip-based SoC. | ||
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For documentation on Constellation, see its `documentation pages <http://constellation.readthedocs.io>`__. |
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What is espresso? Is this like graalvm?
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https://github.com/chipsalliance/espresso .
Espresso is a logic minimizer that Constellation calls (through chisel3) to generate routing tables.
If
espresso
is not installed, the generator falls back on a slower implementation.There was a problem hiding this comment.
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I'm inclined to just add this installation in
build-toolchains-extra.sh
and add a flag to skip this if users don't want it.There was a problem hiding this comment.
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I'm going to leave it in like this for now, to avoid more churn on the install scripts.
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Sure. Can you make an issue so this is noted and we can put it into the next release? I get the feeling that majority of people won't have this installed and will complain about slowness
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Sure, I added an issue. There has been discussion of packaging espresso as a Scala library so it can just be added as a SBT dependency to Chisel, but I don't think there's been any progress on that.
Also, the performance improvement is only apparent for large many core designs, which are still slow to elaborate due to the cost of elaborating many cores.