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Add support for NoC based interconnect with Constellation #1224

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5 changes: 4 additions & 1 deletion .github/scripts/defaults.sh
Original file line number Diff line number Diff line change
Expand Up @@ -28,8 +28,9 @@ declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket chipyard-nomem-scratchpad"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
grouping["group-accels"]="chipyard-fftgenerator chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
grouping["group-other"]="icenet testchipip"
grouping["group-other"]="icenet testchipip constellation"
grouping["group-fpga"]="arty vcu118"

# key value store to get the build strings
Expand Down Expand Up @@ -58,7 +59,9 @@ mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
mapping["chipyard-fftgenerator"]=" CONFIG=FFTRocketConfig"
mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"

mapping["constellation"]=" SUB_PROJECT=constellation"
mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
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7 changes: 7 additions & 0 deletions .github/scripts/remote-do-rtl-build.sh
Original file line number Diff line number Diff line change
Expand Up @@ -18,6 +18,13 @@ cd $REMOTE_CHIPYARD_DIR
./scripts/init-submodules-no-riscv-tools.sh --skip-validate
./scripts/init-fpga.sh


# Constellation can run without espresso, but this improves
# elaboration time drastically
pushd $REMOTE_CHIPYARD_DIR/generators/constellation
scripts/install-espresso.sh $RISCV
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What is espresso? Is this like graalvm?

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https://github.com/chipsalliance/espresso .

Espresso is a logic minimizer that Constellation calls (through chisel3) to generate routing tables.
If espresso is not installed, the generator falls back on a slower implementation.

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I'm inclined to just add this installation in build-toolchains-extra.sh and add a flag to skip this if users don't want it.

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I'm going to leave it in like this for now, to avoid more churn on the install scripts.

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Sure. Can you make an issue so this is noted and we can put it into the next release? I get the feeling that majority of people won't have this installed and will complain about slowness

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Sure, I added an issue. There has been discussion of packaging espresso as a Scala library so it can just be added as a SBT dependency to Chisel, but I don't think there's been any progress on that.

Also, the performance improvement is only apparent for large many core designs, which are still slow to elaborate due to the cost of elaborating many cores.

popd

if [ $1 = "group-accels" ]; then
pushd $REMOTE_CHIPYARD_DIR/generators/gemmini/software
git submodule update --init --recursive gemmini-rocc-tests
Expand Down
6 changes: 6 additions & 0 deletions .github/scripts/run-tests.sh
Original file line number Diff line number Diff line change
Expand Up @@ -102,12 +102,18 @@ case $1 in
make -C $LOCAL_CHIPYARD_DIR/tests
make -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/fft.riscv run-binary-fast
;;
chipyard-constellation)
run_bmark ${mapping[$1]}
;;
icenet)
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
;;
testchipip)
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
;;
constellation)
make run-binary-fast BINARY=none -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]}
;;
*)
echo "No set of tests for $1. Did you spell it right?"
exit 1
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106 changes: 97 additions & 9 deletions .github/workflows/chipyard-run-tests.yml
Original file line number Diff line number Diff line change
Expand Up @@ -261,6 +261,28 @@ jobs:
with:
group-key: "group-cores"

prepare-chipyard-constellation:
name: prepare-chipyard-constellation
needs: setup-complete
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Build RTL on self-hosted
uses: ./.github/actions/prepare-rtl
with:
group-key: "group-constellation"

prepare-chipyard-peripherals:
name: prepare-chipyard-peripherals
needs: setup-complete
Expand Down Expand Up @@ -861,6 +883,53 @@ jobs:
group-key: "group-other"
project-key: "testchipip"

constellation-run-tests:
name: constellation-run-tests
needs: prepare-chipyard-other
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-other"
project-key: "constellation"

chipyard-constellation-run-tests:
name: chipyard-constellation-run-tests
needs: prepare-chipyard-constellation
runs-on: self-hosted
steps:
- name: Delete old checkout
run: |
ls -alh .
rm -rf ${{ github.workspace }}/* || true
rm -rf ${{ github.workspace }}/.* || true
ls -alh .
- name: Checkout
uses: actions/checkout@v3
- name: Git workaround
uses: ./.github/actions/git-workaround
- name: Create conda env
uses: ./.github/actions/create-conda-env
- name: Run tests
uses: ./.github/actions/run-tests
with:
group-key: "group-constellation"
project-key: "chipyard-constellation"


firesim-run-tests:
name: firesim-run-tests
needs: setup-complete
Expand Down Expand Up @@ -939,16 +1008,35 @@ jobs:
# When adding new top level jobs, please add them to `needs` below
all_tests_passed:
name: "all tests passed"
needs: [commit-on-master-check, tutorial-setup-check, documentation-check,
chipyard-rocket-run-tests, chipyard-hetero-run-tests, chipyard-boom-run-tests, chipyard-cva6-run-tests, chipyard-ibex-run-tests,
chipyard-sodor-run-tests, chipyard-dmirocket-run-tests, chipyard-spiflashwrite-run-tests, chipyard-fftgenerator-run-tests,
chipyard-spiflashread-run-tests, chipyard-lbwif-run-tests, chipyard-sha3-run-tests,
chipyard-streaming-fir-run-tests, chipyard-streaming-passthrough-run-tests, chipyard-hwacha-run-tests,
chipyard-gemmini-run-tests, chipyard-nvdla-run-tests,
tracegen-boom-run-tests, tracegen-run-tests,
icenet-run-tests, testchipip-run-tests,
needs: [commit-on-master-check,
tutorial-setup-check,
documentation-check,
chipyard-rocket-run-tests,
chipyard-hetero-run-tests,
chipyard-boom-run-tests,
chipyard-cva6-run-tests,
chipyard-ibex-run-tests,
chipyard-sodor-run-tests,
chipyard-dmirocket-run-tests,
chipyard-spiflashwrite-run-tests,
chipyard-fftgenerator-run-tests,
chipyard-spiflashread-run-tests,
chipyard-lbwif-run-tests,
chipyard-sha3-run-tests,
chipyard-streaming-fir-run-tests,
chipyard-streaming-passthrough-run-tests,
chipyard-hwacha-run-tests,
chipyard-gemmini-run-tests,
chipyard-nvdla-run-tests,
chipyard-constellation-run-tests,
tracegen-boom-run-tests,
tracegen-run-tests,
icenet-run-tests,
testchipip-run-tests,
constellation-run-tests,
prepare-chipyard-fpga, # firesim-run-tests,
fireboom-run-tests, firesim-multiclock-run-tests]
fireboom-run-tests,
firesim-multiclock-run-tests]
runs-on: ubuntu-latest
steps:
- run: echo Success!
1 change: 1 addition & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -21,3 +21,4 @@ env-riscv-tools.sh
env-esp-tools.sh
.bsp/
.conda-env/
.#*
3 changes: 3 additions & 0 deletions .gitmodules
Original file line number Diff line number Diff line change
Expand Up @@ -127,3 +127,6 @@
[submodule "toolchains/libgloss"]
path = toolchains/libgloss
url = https://github.com/ucb-bar/libgloss-htif.git
[submodule "generators/constellation"]
path = generators/constellation
url = https://github.com/ucb-bar/constellation.git
8 changes: 7 additions & 1 deletion build.sbt
Original file line number Diff line number Diff line change
Expand Up @@ -148,7 +148,13 @@ lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator)
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
constellation)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

lazy val constellation = (project in file("generators/constellation"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)

Expand Down
2 changes: 1 addition & 1 deletion docs/Advanced-Concepts/Top-Testharness.rst
Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ We also see this class define several ``ElaborationArtefacts``, files emitted af
Subsystem
^^^^^^^^^^^^^^^^^^^^^^^^^

Looking in `generators/chipyard/src/main/scala/Subsystem.scala <https://github.com/ucb-bar/chipyard/blob/master/generators/chipyard/src/main/scala/Subsystem.scala>`__, we can see how Chipyard's ``Subsystem``
Looking in `generators/chipyard/src/main/scala/Subsystem.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/Subsystem.scala>`__, we can see how Chipyard's ``Subsystem``
extends the ``BaseSubsystem`` abstract class. ``Subsystem`` mixes in the ``HasBoomAndRocketTiles`` trait that
defines and instantiates BOOM or Rocket tiles, depending on the parameters specified.
We also connect some basic IOs for each tile here, specifically the hartids and the reset vector.
Expand Down
3 changes: 3 additions & 0 deletions docs/Chipyard-Basics/Chipyard-Components.rst
Original file line number Diff line number Diff line change
Expand Up @@ -47,6 +47,9 @@ Accelerators
System Components:
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

**constellation**
A generator for network-on-chip (NoC) interconnects.

**icenet**
A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.

Expand Down
34 changes: 34 additions & 0 deletions docs/Customization/NoC-SoCs.rst
Original file line number Diff line number Diff line change
@@ -0,0 +1,34 @@
SoCs with NoC-based Interconnects
==================================

The primary way to integrate a network-on-chip into a Chipyard SoC is to map one of the standard TileLink crossbar-based buses (System Bus, Memory Bus, Control Bus, etc.) to a Constellation-generated NoC.

The interconnect can be mapped as a "private" interconnect for the TileLink bus, in which case a dedicated interconnect to carry the bus traffic will be generated.
Alternatively, the interconnect can be mapped to a shared global interconnect, in which case multiple TileLink buses can be transported over a single shared interconnect.

Private Interconnects
---------------------
An example of integrating dedicated private interconnects for the System Bus, Memory Bus, and Control Bus can be seen in the ``MultiNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/config/NoCConfigs.scala>`__.

.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala
:language: scala
:start-after: DOC include start: MultiNoCConfig
:end-before: DOC include end: MultiNoCConfig

Note that for each bus (``Sbus`` / ``Mbus`` / ``Cbus``), the configuration fragment provides both a parameterization of the private NoC, as well as a mapping between TileLink agents and physical NoC nodes.

For more information on how to construct the NoC parameters, see the `Constellation documentation <http://constellation.readthedocs.io>`__.


Shared Global Interconnect
---------------------------
An example of integrating a single global interconnect that supports transporting multiple TileLink buses can be seen in the ``SharedNoCConfig`` of `generators/chipyard/src/main/scala/config/NoCConfigs.scala <https://github.com/ucb-bar/chipyard/blob/main/generators/chipyard/src/main/scala/config/NoCConfigs.scala>`__.

.. literalinclude:: ../../generators/chipyard/src/main/scala/config/NoCConfigs.scala
:language: scala
:start-after: DOC include start: SharedNoCConfig
:end-before: DOC include end: SharedNoCConfig

Note that for each bus, the configuration fragment provides only the mapping between TileLink agents and physical NoC nodes, while a separate fragement provides the configuration for the global interconnect.

For more information on how to construct the NoC parameters, see the `Constellation documentation <http://constellation.readthedocs.io>`__.
5 changes: 4 additions & 1 deletion docs/Customization/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,9 @@ Customization

These guides will walk you through customization of your system-on-chip:

- Contructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system.
- Constructing heterogenous systems-on-chip using the existing Chipyard generators and configuration system.

- Constructing SoCs with a NoC (network-on-chip) based interconnect using Constellation

- How to include your custom Chisel sources in the Chipyard build system

Expand Down Expand Up @@ -36,6 +38,7 @@ We recommend reading all these pages in order. Hit next to get started!
:caption: Customization:

Heterogeneous-SoCs
NoC-SoCs
Custom-Chisel
Custom-Core
RoCC-or-MMIO
Expand Down
17 changes: 17 additions & 0 deletions docs/Generators/Constellation.rst
Original file line number Diff line number Diff line change
@@ -0,0 +1,17 @@
Constellation
========================

.. image:: ../_static/images/bigsoc.svg

`Constellation <https://github.com/ucb-bar/constellation>`__ is a Chisel NoC RTL generator framework designed from the ground up to support integration in a heterogeneous SoC and evaluation of highly irregular NoC architectures.

- Constellation generates **packet-switched wormhole-routed networks with virtual networks and credit-based flow control**
- Constellation supports **arbitrary directed graph network topologies**, including **irregular** and **hierarchical** network topologies
- Constellation includes a **routing algorithm verifier and routing-table compiler**, which can verify and generate deadlock-free routing tables for arbitrary topologies
- Constellation is a **protocol-independent transport layer**, yet is capable of compliant deadlock-free transport of protocols like **AXI-4** and **TileLink**
- Constellation supports drop-in **integration in Chipyard/Rocketchip SoCs**
- Constellation is **rigorously tested**, with almost 100 different tests across as many network configurations

Constellation is fully integrated into Chipyard, and can be used to generate almost any interconnect in a Chipyard/Rocketchip-based SoC.

For documentation on Constellation, see its `documentation pages <http://constellation.readthedocs.io>`__.
1 change: 1 addition & 0 deletions docs/Generators/index.rst
Original file line number Diff line number Diff line change
Expand Up @@ -21,6 +21,7 @@ so changes to the generators themselves will automatically be used when building
Rocket-Chip
Rocket
BOOM
Constellation
Hwacha
Gemmini
IceNet
Expand Down
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