Bump Verilator to v4.224

[vighneshiyer]

Verilator v4.034 is difficult to build on modern distros since it requires a specific version of bison. The most recent Verilator release is v4.224 - I have tested it locally with RocketConfig and the ISA tests + benchmarks and everything seems to work. Let's see what CI says. If this works, I'll bump the Verilator version in the docs too.

Related PRs / Issues:

Type of change:

• Bug fix
• New feature
• Other enhancement

Impact:

• RTL change
• Software change (RISC-V software)
• Build system change
• Other

Contributor Checklist:

• Did you set main as the base branch?
• Is this PR's title suitable for inclusion in the changelog and have you added a changelog:<topic> label?
• Did you state the type-of-change/impact?
• Did you delete any extraneous prints/debugging code?
• Did you mark the PR with a changelog: label?
• (If applicable) Did you add documentation for the feature?
• (If applicable) Did you add a test demonstrating the PR?

• (If applicable) Did you mark the PR as Please Backport?

[vighneshiyer]

Looks like -O1 also fails and using -O0 produces a very slow simulator (which may be acceptable for now). We should investigate further by bumping Verilator in the CVA6 repo.

On the SPI side, I have isolated the bug to the snippet assigning dq_{0,1,2,3} in SimSPIFlashModel.sv. There seems to be a Verilator regression when dealing with inter-module tristate nets (possibly this issue: verilator/verilator#3399). I am working on creating a minimal standalone example and finding the culprit commit in veriator by bisecting.

[abejgonzalez]

Looks like -O1 also fails and using -O0 produces a very slow simulator (which may be acceptable for now). We should investigate further by bumping Verilator in the CVA6 repo.

On the SPI side, I have isolated the bug to the snippet assigning dq_{0,1,2,3} in SimSPIFlashModel.sv. There seems to be a Verilator regression when dealing with inter-module tristate nets (possibly this issue: verilator/verilator#3399). I am working on creating a minimal standalone example and finding the culprit commit in veriator by bisecting.

I think -O0 is fine for now. If we want to we can also try to mess around by disabling different optimizations (-fno-* flags).

[vighneshiyer]

@abejgonzalez The recently released Verilator v4.226 fixes the issues with the SPI testbench: confirmed locally. I pushed a bump to check CI for the other tests too. CVA6 still segfaults right after the simulation is initialized (after DRAMSim2 init, maybe when eval() is called).

[abejgonzalez]

Closing since this is solved by #1163 now