Merge pull request #1435 from ucb-bar/blockserialtl

Bump TestChipIp to improve default serial_tl behavior
ucb-bar · Apr 18, 2023 · 3b303ba · 3b303ba
2 parents cf0db30 + ad9ea33
commit 3b303ba
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Showing 2 changed files with 1 addition and 2 deletions.
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -39,7 +39,6 @@ class ChipLikeQuadRocketConfig extends Config(
   new chipyard.config.WithCbusToPbusCrossingType(AsynchronousCrossing()) ++  // Add Async crossing between PBUS and CBUS
   new chipyard.config.WithSbusToMbusCrossingType(AsynchronousCrossing()) ++  // Add Async crossings between backside of L2 and MBUS
   new testchipip.WithAsynchronousSerialSlaveCrossing ++                      // Add Async crossing between serial and MBUS. Its master-side is tied to the FBUS
-  new testchipip.WithSerialTLAsyncResetQueue ++                              // Add Async reset queue to block ready while in reset
 
   new chipyard.config.AbstractConfig)
 
diff --git a/generators/testchipip b/generators/testchipip