SystemVerilog implementations of a 101 pattern detector using both structural and behavioral modeling styles. Includes separate testbenches for each implementation. Designed for detecting overlapping 101 patterns in a serial bitstream, useful for learning FSM design and simulation in digital systems.
fsm pattern detector verilog vivado systemverilog testbench system-verilog digital-circuit digital-design 101 xilinx-vivado pattern-detector digital-system
-
Updated
Jun 9, 2025 - SystemVerilog