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hdl

Verilog is a widely-used hardware description language (HDL) that enables designers to model, simulate, and synthesize digital circuits. It provides a text-based format for specifying the structure and behavior of electronic systems, making it easier to design complex hardware components such as microprocessors, memory, and communication devices.

Here are 83 public repositories matching this topic...

amaranth-lang / amaranth

A modern hardware definition language and toolchain based on Python

fpga hdl amaranth-hdl

Updated Sep 4, 2025
Python

m-labs / nmigen

A refreshed Python toolbox for building complex digital hardware. See https://gitlab.com/nmigen/nmigen

fpga hdl yosys nmigen

Updated Jan 8, 2022
Python

pymtl / pymtl3

Pymtl 3 (Mamba), an open-source Python-based hardware generation, simulation, and verification framework

python rtl verilog systemverilog hdl open-source-hardware pymtl hardware-generation open-source-eda multi-level-modeling cycle-level-modeling

Updated Aug 24, 2025
Python

UCSBarchlab / PyRTL

A collection of classes providing simple hardware specification, simulation, tracing, and testing suitable for teaching and research. Simplicity, usability, clarity, and extensibility are the overarching goals, rather than performance or optimization.

python rtl hdl pyrtl

Updated Aug 6, 2025
Python

suoto / hdl_checker

Repurposing existing HDL tools to help writing better code

Updated Jun 6, 2024
Python

kevinpt / symbolator

HDL symbol generator

vhdl verilog symbol hdl

Updated Feb 2, 2023
Python

google / pcbdl

PCB Design Language: A programming way to design schematics.

python hardware electronics eda schematics hdl netlist

Updated Apr 8, 2021
Python

bogdanvuk / pygears

HW Design: A Functional Approach

python design functional simulator asic fpga hardware hdl

Updated Jun 26, 2023
Python

mciepluc / cocotb-coverage

Functional Coverage and Constrained Randomization Extensions for Cocotb

verification hdl cocotb mdv

Updated Nov 15, 2023
Python

cocotb / cocotb-bus

Pre-packaged testbenching tools and reusable bus interfaces for cocotb

interface bus vhdl verilog hdl testbench cocotb

Updated Aug 1, 2025
Python

sphinxcontrib-hdl-diagrams

SymbiFlow / sphinxcontrib-hdl-diagrams

Sphinx Extension which generates various types of diagrams from Verilog code.

documentation fpga sphinx documentation-tool rtl verilog diagrams hdl yosys sphinx-extension symbiflow

Updated Sep 25, 2023
Python

icebreaker-fpga / icebreaker-amaranth-examples

This repository contains iCEBreaker examples for Amaranth HDL.

python fpga hardware electronics hdl gateware

Updated Oct 31, 2023
Python

Intuity / forastero

Making cocotb testbenches that bit easier

python simulation verilog systemverilog hdl

Updated Jul 15, 2025
Python

Logicademy / HDLGen-ChatGPT

HDLGen-ChatGPT, works in tandem with ChatGPT chat interface to enable fast digital systems design and test specification capture, and automatic generation of both VHDL and Verilog models, and testbenches, and AMD Vivado and Intel Quartus Electronic Design Automation (EDA) project

python automation fpga xml vhdl verilog xilinx vivado hardware-designs hdl

Updated Oct 28, 2024
Python

m-labs / nmigen-boards

Board and connector definition files for nMigen

fpga hdl nmigen

Updated Sep 22, 2020
Python

eyesoft / home_assistant_buspro

The HDL Buspro integration allows you to control your HDL Buspro system from Home Assistant.

home-assistant hdl buspro

Updated Nov 7, 2024
Python

peteut / migen-axi

AXI support for Migen/MiSoC

hdl misoc migen zynq-7000

Updated Jun 5, 2025
Python

charlottia / hdx

HDL development environment on Nix.

nix fpga hdl yosys nextpnr amaranth-hdl

Updated Oct 23, 2024
Python

sphinx-verilog-domain

SymbiFlow / sphinx-verilog-domain

Sphinx domain to allow integration of Verilog / SystemVerilog documentation into Sphinx.

sphinx rtl verilog systemverilog hdl verilog-library sphinx-extension sphinx-domain

Updated Mar 1, 2021
Python

torii-hdl

shrine-maiden-heavy-industries / torii-hdl

A Python-based HDL and framework for silicon-based witchcraft

fpga hdl yosys digital-logic-design nextpnr asic-design torii-hdl

Updated Sep 10, 2025
Python

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Website: github.com/topics/verilog
Wikipedia: Wikipedia