IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Technische Universität Dresden, Germany

Implementation of a Tensor Processing Unit for embedded systems and the IoT.

VHDL Guide

The PicoBlaze-Library offers several PicoBlaze devices and code routines to extend a common PicoBlaze environment to a little System on a Chip (SoC or SoFPGA).

A list of VHDL codes implementing cryptographic algorithms

Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.

MIPS Pipelined CPU simulation using VHDL language

FPGA based frequnecy counter hard- and software repository

An 8-bit processor in VHDL based on a simple instruction set

all projects of vhdl course of university

Deluxe RISC processor

Advanced Computer Architecture at EPFL.

Microprocessor without Interlocked Pipelined Stages (MIPS) architectures implemented in single-cycle and multi-cycle formats.

Two Address Instructions (16bit) CPU

NEANDER - A basic theorical computer

Contains VHDL netlists of basic digital circuits

Design & Verification of IP Cores and ICs, Artificial Intelligence

🏄 Custom IP for vector operations

VHDL implementation of the WiSARD Neural Network (Wilkie, Stoneham and Aleksander Recognition Device)

This Repository contains custom-defined (AUBIE) processor components as defined by the ModelSimPE VHDL([Very High Speed Integrated Circuit] Hardware Description Language) Simulation Environment