4×4 7-bit matrix multiplication hardware accelerator using a systolic array, with a Python driver for the Basys 3 FPGA and a systolic array UVC using UVM.
fpga rtl matrix-multiplication verilog python-driver systemverilog hdl uvm uvc 8bit digital-design basys3 hardware-verification hardware-accelerator systolic-array
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Updated
Sep 2, 2025 - SystemVerilog