Custom standard logic gates and flip-flops cell designed in Cadence Virtuoso using GPDK090 CMOS technology library. Build, testbench and evaluation
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Jan 9, 2026 - Verilog
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gpdk090
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90 nm two-stage CMOS op-amp with Miller compensation and AC, transient, load and stability characterization.
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Jul 26, 2026 - Python
Current-Starved Ring Oscillator PUF in 90nm CMOS — analog design in Cadence Virtuoso with behavioral verification in Vivado. Samsung Chip Design Studio project.
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Jul 5, 2026 - Verilog
90 nm positive-feedback OTA ring-VCO research with architecture screening, practical current mirrors and tuning-range analysis.
spectre feedback-systems vlsi cadence-virtuoso cmos analog-design ring-oscillator voltage-controlled-oscillator current-mirror gpdk090
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Jul 26, 2026 - Python
1.2 V two-stage Miller OTA in 90 nm CMOS — 67 dB, 49 MHz, 279 µW. Hand-derived compensation, 12-corner PVT, 500-point Monte Carlo.
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Aug 6, 2026
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