tinyGPU: A Predicated-SIMD processor implementation in SystemVerilog
-
Updated
Jul 14, 2021 - SystemVerilog
#
computer-organization
Here are 3 public repositories matching this topic...
RISC-V 5-Stage Pipeline CPU, Semester Project of CS202 Computer Organization
-
Updated
Dec 30, 2024 - SystemVerilog
A SystemVerilog implementation of a 4-bit unsigned array multiplier using structural design. The module computes an 8-bit product from two 4-bit binary inputs by generating partial products and summing them using full adders. Ideal for learning digital design fundamentals and testing with simulators or FPGA synthesis tools.
design digital array verilog systemverilog vlsi testbench system-verilog digital-design computer-organization xilinx-vivado multiplier digital-system-design array-multiplier
-
Updated
May 29, 2025 - SystemVerilog
Improve this page
Add a description, image, and links to the computer-organization topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the computer-organization topic, visit your repo's landing page and select "manage topics."