32KB 4-Way Set-Associative L1 Cache Controller with Non-Blocking MSHR, Tree-PLRU, and AXI4 Refills targeting SkyWater 130nm.
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Updated
Aug 19, 2026 - SystemVerilog
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cache-controller
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RTL implementation and class-based verification of a Direct-Mapped Cache Controller using SystemVerilog with a self-checking scoreboard, directed and constrained-random testing.
verification systemverilog computer-architecture vlsi testbench digital-design cache-controller rtl-design-and-verification class-based-verification
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Jul 28, 2026 - SystemVerilog
cache controller verification
cpu fpv cache formal-verification sva cache-miss write-back write-allocate cache-controller direct-mapped-cache cache-hit
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Updated
Sep 8, 2026 - SystemVerilog
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