IC implementation of Systolic Array for TPU
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Oct 21, 2024 - Verilog
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asic-verification
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I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. A single-path delay commutator processing element (SDC PE) has been proposed for the first time. It saves a complex adder compared with the typical radix-2 butterfly unit. The new pipelined architecture can be …
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Dec 3, 2023 - Verilog
End-to-end ASIC SoC design and functional verification of a lightweight machine learning accelerator using SystemVerilog and UVM. Includes Python automation for test generation and result analysis. Built to simulate real-world ML silicon validation at scale.
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Mar 26, 2025 - Verilog
This is a basic RISC-V based processor under development. It follows the 32-bit Integer ISA.
open-source processor-architecture asic fpga verilog hardware-designs vlsi verilog-hdl risc-v riscv32 asic-verification processor-design vlsi-design asic-design openlane openlane-flow
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Apr 4, 2025 - Verilog
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