A simple sram controller and test for the altera DE1 FPGA board
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Updated
Apr 2, 2019 - VHDL
A simple sram controller and test for the altera DE1 FPGA board
Integrated and programmed a VGA Interface using the Altera DE1 to output in synchronization with a custom programmed finite-state machine.
The Snake Game Made in VHDL for Altera DE1 using Quartus V.13
Simple seven segment display controller for the 4 seven segment displays for the terasic de1 altera board
Kitchen-timer on Altera DE1 FPGA development kit - VHDL
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