This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone benchmark value: 1.2 DMIPS/MHz. It could be utilized in your FPGA design as one submodule, if you master the interface of this .v file. This IP core is very compact. It is one .v file and has only less 1800 lines.

Verilog Implementation of a 32-bit Multicycle CPU

A RISC-V Single Cycle Processor which is done in verilog.

MIPS Architecture 32 bit CPU in Verilog Quartus

The algorithm proposes a prototype to design a 32-bit processor. The processor is capable of performing the task which includes fetching the instructions, decoding the instructions to figure out what operation needs to be performed, on what operands it needs to perform and where to store, write, the result obtained.

An implementation of a 32-bit DLX(a derivative of MIPS) architecture based RISC processor in verilog

Architecure for the Data path and Controller as well as Hazard Units for a 32 bit ARM based Single Cycle, Multi Cycle and Pipelined Based Processor

bus interface, integrating LFSR’s for streamlined register management. Enabled seamless master-peripheral communication, enhancing system efficiency. Orchestrated comprehensive design stages, yielding a versatile RTL architecture for diverse applications

procesador monociclo en verilog tipo MIPS