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Brnch:syncMem Trgt:chisel
Time elapsed: 50 minutes, 5 seconds
Flags: --syncMem --multifile=4 --synth
Chisel.Unit.ArbitraryLambda: Pass
Chisel.Unit.BasicCondFSM: Pass
Chisel.Unit.BasicFSM: Pass
Chisel.Unit.BinaryFileTest: Pass
Chisel.Unit.BlockReduce1D: Pass
Chisel.Unit.BlockReduce2D: Pass
Chisel.Unit.Breakpoint: Pass
Chisel.Unit.BubbledWriteTest: Pass
Chisel.Unit.ChangingCtrMax: Pass
Chisel.Unit.CompactingFifo: Pass
Chisel.Unit.CtrlEnable: Pass
Chisel.Unit.DeviceMemcpy: Pass
Chisel.Unit.DiagBanking: Pass
Chisel.Unit.DotProductFSM: Pass
Chisel.Unit.FifoLoadSRAMStore: Pass
Chisel.Unit.FifoLoadStore: Pass
Chisel.Unit.FifoPushPop: Pass
Chisel.Unit.FifoStackFSM: Pass
Chisel.Unit.FixPtInOutArg: Pass
Chisel.Unit.FixPtMem: Pass
Chisel.Unit.FloatBasics: Pass
Chisel.Unit.HugeTileLoadStore: Pass
Chisel.Unit.IndirectLoad: Pass
Chisel.Unit.InOutArg: Pass
Chisel.Unit.LaneMaskPar: Pass
Chisel.Unit.LittleTypeTest: Pass
Chisel.Unit.LUTTest: Pass
Chisel.Unit.MaskedWrite: Pass
Chisel.Unit.Memcpy2D: Pass
Chisel.Unit.MemTest1D: Pass
Chisel.Unit.MemTest2D: Pass
Chisel.Unit.MixedIOTest: Pass
Chisel.Unit.MultiWriteBuffer: Pass
Chisel.Unit.Niter: Pass
Chisel.Unit.OHM: Fail [Validation]
↳ Cause: Application reported that it did not pass validation.
Chisel.Unit.PageBoundaryTest: Pass
Chisel.Unit.ParFifoLoad: Pass
Chisel.Unit.PartialTileLoadStore: Pass
Chisel.Unit.RetimedFifoBranch: Pass
Chisel.Unit.SequentialWrites: Pass
Chisel.Unit.SimpleFold: Pass
Chisel.Unit.SimpleMemReduce: Pass
Chisel.Unit.SimpleReduce: Pass
Chisel.Unit.SimpleSequential: Pass
Chisel.Unit.SimpleTileLoadStore: Pass
Chisel.Unit.SmallTensorLoad: Pass
Chisel.Unit.SpecialMath: Pass
Chisel.Unit.SSV1D: Pass
Chisel.Unit.SSV2D: Pass
Chisel.Unit.StackLoadStore: Pass
Chisel.Unit.StridedLoad: Pass
Chisel.Unit.Tensor3D: Pass
Chisel.Unit.Tensor4D: Pass
Chisel.Unit.Tensor5D: Pass
Chisel.Unit.UnalignedFifoLoad: Pass
Chisel.Unit.UnalignedLd: Pass
Chisel.Unit.UnalignedTileLoadStore: Pass
Chisel.Unit.UniqueParallelLoad: Pass
Chisel.Dense.AES: Pass
Chisel.Dense.BlockReduce1D: Pass
Chisel.Dense.BTC: Pass
Chisel.Dense.Convolution_FPGA: Pass
Chisel.Dense.Differentiator: Pass
Chisel.Dense.DotProduct: Pass
Chisel.Dense.EdgeDetector: Pass
Chisel.Dense.FFT_Strided: Pass
Chisel.Dense.FFT_Transpose: Pass
Chisel.Dense.FixPtMem: Pass
Chisel.Dense.FloatBasics: Pass
Chisel.Dense.GDA: Pass
Chisel.Dense.GEMM_Blocked: Pass
Chisel.Dense.GEMM_NCubed: Pass
Chisel.Dense.Gibbs_Ising2D: Pass
Chisel.Dense.HALP_handoff: Pass
Chisel.Dense.HALP: Pass
Chisel.Dense.JPEG_Decompress: Pass
Chisel.Dense.JPEG_Markers: Pass
Chisel.Dense.Kmeans: Pass
Chisel.Dense.KMP: Pass
Chisel.Dense.LP_SGD: Pass
Chisel.Dense.LP_SVRG: Pass
Chisel.Dense.MatMult_inner: Pass
Chisel.Dense.MatMult_outer: Pass
Chisel.Dense.MD_Grid: Pass
Chisel.Dense.MD_KNN: Pass
Chisel.Dense.MultiplexedWriteTest: Pass
Chisel.Dense.Niter: Pass
Chisel.Dense.NW: Pass
Chisel.Dense.OuterProduct: Pass
Chisel.Dense.SGD_minibatch: Pass
Chisel.Dense.SGD: Pass
Chisel.Dense.SHA1: Pass
Chisel.Dense.SimpleRowStridedConv: Pass
Chisel.Dense.SingleLayerConv_IRCO: Pass
Chisel.Dense.SingleLayerConv_OIRC: Pass
Chisel.Dense.SingleLayerConv_RCIO: Pass
Chisel.Dense.Sobel: Pass
Chisel.Dense.Sort_Merge: Pass
Chisel.Dense.Sort_Radix: Pass
Chisel.Dense.Stencil2D: Pass
Chisel.Dense.Stencil3D: Pass
Chisel.Dense.SVRG: Pass
Chisel.Dense.SW: Pass
Chisel.Dense.SYRK_col: Pass
Chisel.Dense.Tensor3D: Pass
Chisel.Dense.Tensor4D: Pass
Chisel.Dense.Tensor5D: Pass
Chisel.Dense.TPCHQ6: Pass
Chisel.Dense.TRSM: Pass
Chisel.Dense.Viterbi: Pass
Chisel.Sparse.BFS_Bulk: Pass
Chisel.Sparse.BFS_Queue: Pass
Chisel.Sparse.GatherStore: Pass
Chisel.Sparse.PageRank_Bulk: Pass
Chisel.Sparse.PageRank: Pass
Chisel.Sparse.ScatterGather: Pass
Chisel.Sparse.SPMV_CRS: Pass
Chisel.Sparse.SPMV_ELL: Pass
Chisel.Fixme.Backprop: Pass
Spatial commit
commit 2f9c05ad1bee5102a499f8ec99b03c9a03a153db
Merge: 6fab234 392f5df
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Thu May 3 11:22:42 2018 -0700
Merge remote-tracking branch 'origin/fpga' into develop
commit 392f5dfb9931905636925792c245482b376f2e58
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Thu May 3 11:22:24 2018 -0700
fix new dw sram by reverting to old stuff temporarily, and fix struct transfers
M apps
M argon
M spatial/core/resources/chiselgen/template-level/fringeVCS/DRAM.h
M spatial/core/resources/chiselgen/template-level/fringeVCS/SRAMVerilogSim.v
M spatial/core/src/spatial/codegen/cppgen/CppGenHostTransfer.scala
M spatial/core/src/spatial/codegen/cppgen/CppGenSRAM.scala
Argon commit
commit 61dd9512b2c4193f4831525d3da73b64e24b3c53
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Thu May 3 11:21:45 2018 -0700
add toRaw for structs
M core/src/argon/codegen/cppgen/CppGenStruct.scala
Virtualized commit
commit 05f6c52d98f892ee732cf8c43cd6c336dabc9bf4
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Mon Mar 12 17:51:44 2018 -0700
update build.sbt
M build.sbt
Spatial-Apps commit
commit f2d7e5ce8edcdbdcbcaa67dde5839860b36eec6a
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Thu May 3 11:21:18 2018 -0700
update apps
M src/Regression.scala
M src/Training.scala
Creation Time- 2018-05-03_11-26-50 | Status- debug | Type- chisel | tests- all | User- mattfel | Origin- london | Destination- london | Branch- syncMem | Spatial- 2f9c0 | Argon- 61dd9 | Virtualized- 05f6c | Spatial-apps- f2d7e