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Brnch:arria10 Trgt:chisel
Time elapsed: 59 minutes, 15 seconds
Flags: --multifile=5 --synth
Chisel.Unit.ArbitraryLambda: Pass
Chisel.Unit.BasicCondFSM: Pass
Chisel.Unit.BasicFSM: Pass
Chisel.Unit.BlockReduce1D: Pass
Chisel.Unit.BlockReduce2D: Pass
Chisel.Unit.Breakpoint: Pass
Chisel.Unit.BubbledWriteTest: Pass
Chisel.Unit.ChangingCtrMax: Pass
Chisel.Unit.CompactingFifo: Pass
Chisel.Unit.CtrlEnable: Pass
Chisel.Unit.DeviceMemcpy: Pass
Chisel.Unit.DiagBanking: Pass
Chisel.Unit.DotProductFSM: Pass
Chisel.Unit.FifoLoadSRAMStore: Pass
Chisel.Unit.FifoLoadStore: Pass
Chisel.Unit.FifoPushPop: Pass
Chisel.Unit.FifoStackFSM: Pass
Chisel.Unit.FixPtInOutArg: Pass
Chisel.Unit.FixPtMem: Pass
Chisel.Unit.FloatBasics: Pass
Chisel.Unit.IndirectLoad: Pass
Chisel.Unit.InOutArg: Pass
Chisel.Unit.LaneMaskPar: Pass
Chisel.Unit.LUTTest: Pass
Chisel.Unit.MaskedWrite: Pass
Chisel.Unit.Memcpy2D: Pass
Chisel.Unit.MemTest1D: Pass
Chisel.Unit.MemTest2D: Pass
Chisel.Unit.MixedIOTest: Pass
Chisel.Unit.MultiplexedWriteTest: Pass
Chisel.Unit.MultiWriteBuffer: Pass
Chisel.Unit.Niter: Pass
Chisel.Unit.OHM: Pass
Chisel.Unit.PageBoundaryTest: Pass
Chisel.Unit.ParFifoLoad: Pass
Chisel.Unit.RetimedFifoBranch: Pass
Chisel.Unit.SequentialWrites: Pass
Chisel.Unit.SimpleFold: Pass
Chisel.Unit.SimpleMemReduce: Pass
Chisel.Unit.SimpleReduce: Pass
Chisel.Unit.SimpleSequential: Pass
Chisel.Unit.SimpleTileLoadStore: Pass
Chisel.Unit.SpecialMath: Pass
Chisel.Unit.SSV1D: Pass
Chisel.Unit.SSV2D: Pass
Chisel.Unit.StackLoadStore: Pass
Chisel.Unit.StridedLoad: Pass
Chisel.Unit.Tensor3D: Pass
Chisel.Unit.Tensor4D: Pass
Chisel.Unit.Tensor5D: Pass
Chisel.Unit.UnalignedFifoLoad: Pass
Chisel.Unit.UnalignedLd: Pass
Chisel.Unit.UniqueParallelLoad: Pass
Chisel.Dense.AES: Pass
Chisel.Dense.BasicBLAS: Pass
Chisel.Dense.BTC: Pass
Chisel.Dense.Convolution_FPGA: Pass
Chisel.Dense.Convolutions: Pass
Chisel.Dense.Differentiator: Pass
Chisel.Dense.DotProduct: Pass
Chisel.Dense.EdgeDetector: Pass
Chisel.Dense.FFT_Strided: Pass
Chisel.Dense.FFT_Transpose: Pass
Chisel.Dense.GDA: Pass
Chisel.Dense.GEMM_Blocked: Fail [Execution]
↳ Cause: Execution timed out after 2000 seconds
Chisel.Dense.GEMM_NCubed: Pass
Chisel.Dense.Gibbs_Ising2D: Pass
Chisel.Dense.JPEG_Decompress: Pass
Chisel.Dense.JPEG_Markers: Pass
Chisel.Dense.Kmeans: Pass
Chisel.Dense.KMP: Pass
Chisel.Dense.MatMult_inner: Pass
Chisel.Dense.MatMult_outer: Pass
Chisel.Dense.MD_Grid: Pass
Chisel.Dense.MD_KNN: Pass
Chisel.Dense.NW: Pass
Chisel.Dense.OuterProduct: Pass
Chisel.Dense.SGD_minibatch: Pass
Chisel.Dense.SGD: Pass
Chisel.Dense.SHA1: Pass
Chisel.Dense.SimpleRowStridedConv: Pass
Chisel.Dense.Sobel: Pass
Chisel.Dense.Sort_Merge: Pass
Chisel.Dense.Sort_Radix: Pass
Chisel.Dense.Stencil2D: Pass
Chisel.Dense.Stencil3D: Pass
Chisel.Dense.SW: Pass
Chisel.Dense.SYRK_col: Pass
Chisel.Dense.TPCHQ6: Pass
Chisel.Dense.TRSM: Pass
Chisel.Dense.Viterbi: Pass
Chisel.Sparse.BFS_Bulk: Pass
Chisel.Sparse.BFS_Queue: Pass
Chisel.Sparse.GatherStore: Pass
Chisel.Sparse.PageRank_Bulk: Pass
Chisel.Sparse.PageRank: Pass
Chisel.Sparse.ScatterGather: Pass
Chisel.Sparse.SPMV_CRS: Pass
Chisel.Sparse.SPMV_ELL: Pass
Chisel.Fixme.Backprop: Pass
Chisel.Fixme.SPMV_DumbPack: Fail [Execution]
↳ Cause: Execution timed out after 2000 seconds
Spatial commit
commit 211570d2325b6591dc54a7a670af73adbd59eeb6
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Jan 29 13:55:21 2018 -0800
updated addressmap of arria10 so that memory starts from 0x20000000
M bin/arria10_debuggers/read_sdram_hps.c
M bin/arria10_debuggers/test_arria10.sh
M spatial/core/resources/cppgen/fringeArria10/Arria10AddressMap.h
Argon commit
commit dfdda6bd2d1e4a88e1ac26a52d1fc9ae3e9532c2
Merge: dd8ba76 578f2f6
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Sat Jan 27 12:57:32 2018 -0800
Merge branch 'develop' of https://github.com/stanford-ppl/argon into arria10
commit 578f2f6d0981f31e40d3e29fd5b6f8c4b5473025
Author: David Koeplinger <dkoeplinger@gmail.com>
Date: Tue Jan 23 19:55:41 2018 -0800
Fix CSE across unrelated type casts
M core/src/argon/core/cake/LayerStaging.scala
M core/src/argon/lang/FixPt.scala
M core/src/argon/lang/FltPt.scala
M core/src/argon/nodes/FixPt.scala
M core/src/argon/nodes/FltPt.scala
commit ce91373df000c88b96f3cdaacd13825f02161683
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Mon Jan 22 19:52:20 2018 -0800
add asic back in
M core/src/argon/codegen/chiselgen/ChiselCodegen.scala
commit c1e6932c7f1dcc943f58a876402a3ba534f94f6e
Merge: f8911cb 27f3e3c
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Mon Jan 22 19:48:19 2018 -0800
Merge remote-tracking branch 'origin/arria10' into fpga
Virtualized commit
commit 1a5adc8e9cd171f1a8c3f1f66dddbc04d89aa51f
Author: David Koeplinger <dkoeplinger@gmail.com>
Date: Fri Jul 21 17:15:08 2017 -0700
fix mistake in Structs
M src/org/virtualized/Structs.scala
Spatial-Apps commit
commit 4a738c3daa770433a56ce72a44cc7a3fd6dde462
Merge: 11ff39f 3a8f809
Author: David Koeplinger <dkoeplinger@gmail.com>
Date: Tue Jan 23 19:49:39 2018 -0800
resolve conflicts
commit 3a8f80969a2a2adb8e9de0d1099cd9f64492c7ea
Author: Matthew <mattfel@stanford.edu>
Date: Tue Jan 23 12:11:04 2018 -0800
runinng compile
M src/Regression.scala
commit b8b21d7e53eb8948d6cb868bdd8d8f5ca70932c0
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Tue Jan 23 10:34:38 2018 -0800
add second mem to make pageboundarytest harder
M src/UnitTests.scala
commit 03886b1c95f05bd118882166c116c7f2b9f1a1a0
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Jan 22 19:58:34 2018 -0800
updated products
M src/Products.scala
commit 8571cb7308b0a9b02134e3a77b931cff75a523d3
Merge: b5500f2 77f47a0
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Jan 22 19:55:10 2018 -0800
merged apps
commit b5500f296e8fc1d814bf680505c79fc8195c67e9
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Jan 22 19:40:54 2018 -0800
start merging with regression branch
M src/BasicMemoryTests.scala
M src/DotProductShowCase.scala
commit 77f47a028b6016d15079bf38129f29558a134ef3
Author: Matthew Feldman <mattfel@stanford.edu>
Date: Mon Jan 22 17:07:22 2018 -0800
add arria10 to reg
M src/Regression.scala
commit 0f40cab061c7ddf9b4a758e6fc70827f263ca1a1
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Jan 22 16:28:43 2018 -0800
working on apps for ee109 demo
M src/BasicMemoryTests.scala
A src/DotProductShowCase.scala
commit 0edcc34dac94a8aea88626dd39b99408dcef5c3e
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Fri Jan 19 17:24:00 2018 -0800
added some more tests for basic dram ops
A src/BasicMemoryTests.scala
commit 6c26c8ea170f0dac2f134babb41b7bd34acc30a9
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Thu Jan 18 21:22:52 2018 -0800
added some memory tests
M src/MemoryTests.scala
commit f6f7b606c7cfc37d2be59ac08c97a96f2ee045a3
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Wed Jan 17 22:41:41 2018 -0800
SRAMTest passed on arria10soc
M src/MemoryTests.scala
commit 7e35c7abe9f891f91961b04b917c829efcce00b0
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Wed Jan 17 22:41:14 2018 -0800
updated memory tests with a reduce of fpga mem
M src/MemoryTests.scala
commit 0999e23ea7755cab6bb0e0ec730774fb969d58fb
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Wed Jan 17 21:45:58 2018 -0800
added apps for memory tests
A src/MemoryTests.scala
commit 230fe2b79a3ef2111576beb91b4a34953aecbc7c
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Wed Jan 17 21:45:48 2018 -0800
added apps for memory tests
M src/InOutArg.scala
commit 5e6be72265df447e1a4041699194241a1b59ff51
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Wed Jan 17 13:52:25 2018 -0800
testing one app a time
A examples/ArgInOut.scala
A examples/BLAS3.scala
A examples/BankingTests.scala
A examples/CHStone.scala
A examples/Classics.scala
A examples/MachSuite.scala
A examples/MatMults.scala
A examples/MiniParticleFilter.scala
A examples/Products.scala
A examples/RaoBlackParticleFilter.scala
A examples/Rasters.scala
A examples/Regression.scala
A examples/SILIComm.scala
A examples/StreamInOutAdd.scala
A examples/UnitTests.scala
A examples/Videos.scala
A src/InOutArg.scala
commit 415432970269436f467d51289c78c76b4b029b8a
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Wed Jan 17 13:52:13 2018 -0800
for testing purposes
D src/ArgInOut.scala
D src/BLAS3.scala
D src/BankingTests.scala
D src/CHStone.scala
D src/Classics.scala
D src/MachSuite.scala
D src/MatMults.scala
D src/MiniParticleFilter.scala
D src/Products.scala
D src/RaoBlackParticleFilter.scala
D src/Rasters.scala
D src/Regression.scala
D src/SILIComm.scala
D src/StreamInOutAdd.scala
D src/UnitTests.scala
D src/Videos.scala
commit f098c7fdc8c24d0bed40a6fbb6a736af1e9ea6b5
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Jan 15 15:18:11 2018 -0800
removed bandwidthtest for now
D src/BandwidthTests.scala
commit 88af49d09d3f365f33dbba7c6f5653f088ca92d6
Merge: 58cfb9d 53fb359
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Thu Jan 11 15:49:52 2018 -0800
merged with develop
commit 58cfb9d9cc0f0e1caae00d0f76bdecaa3bed59cd
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Thu Jan 11 15:33:48 2018 -0800
added sramtest
M src/UnitTests.scala
commit 1926533ec9b685e86f4fdee354816fc226801aa0
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Dec 18 20:09:15 2017 -0800
added test case for DRAMWrite
M src/UnitTests.scala
commit 1c8a735588df311a2f6f8a8ddd464bd844fce81a
Author: kelayamatoz <zhaotian1991713@gmail.com>
Date: Mon Dec 18 18:30:49 2017 -0800
adding tests for simple dram interfaces
M src/UnitTests.scala
Creation Time- 2018-01-29_13-58-50 | Status- debug | Type- chisel | tests- all | User- tianzhao | Origin- tucson | Destination- london | Branch- arria10 | Spatial- 21157 | Argon- dfdda | Virtualized- 1a5ad | Spatial-apps- 4a738